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RM41L232: Level 2/Level 3(L2/L3) Interconnect

lina zhang
Intellectual 370 points
Part Number: RM41L232

Hello,

 Level 2/Level 3(L2/L3) Interconnect described in safety manual of RM41Lx,  what is it?which bus in MCU?

Also, one of its safety features is [INC3:Information Redundancy], and how do we realize this diagnostic in the software of my system?

Thanks.

  • 0
    TI__Guru**** 186196 points

    Hello Lily,

    This is a screenshot of Architectural Block Diagram TRM:

    I marked up L1 (red box), L2(blue box) and L3 (yellow box). All the peripherals are on L3. Each peripheral has its own connection to PCR, so the PCR is the interconnect.

    L2/L3 information redundancy:

    • Read back of known data from peripheral modules multiple times and compare.
    • Internal loop back with data transmitted through L2/L3 and read back for comparison.
    • CRC from read back data can also be compared with the computed CRC of transmit data.

    Regards,

    QJ

  • 0 in reply to QJ Wang
    Intellectual 370 points
    Thank you very much for the reply.
    And again I have a question about L2L3 interconnect diagnositc.
    I am using Reg_Read_compare from register_read_back file in demo app project to realize [INC4:Periodic software readback of static configuration registers] in safety manual.But when enabling L2L3_ENABLED macro definition, compile errors happened and showed that 'l2l3_config_reg_t is undefined'.
    and so which registers does l2l3_config_reg_t structure contain?
    Is it necessary to define the l2l3_config_reg_t structure by ourself?
  • 0 in reply to lina zhang
    TI__Guru**** 186196 points

    Hi Lily,

    You can define the l2l3_config_reg_t structure in sys_pcr.h. It is similar to pcr_config_reg_t. This is my understanding, I will check with the developer of SafeTI Library.

    The PCR manages the accesses to the peripheral registers and peripheral controller memories. It provides a global reset for all the peripherals. It also supports the capability to selectively enable or disable the clock for each peripheral individually. The PCR also manages the accesses to the system module registers required to configure the device’s clocks, interrupts, and so on.

    For example:

    typedef struct  l2l3_config_reg

    {

       uint32 CONFIG_PMPROTSET0;

       uint32 CONFIG_PMPROTSET1;

       uint32 CONFIG_PPROTSET0;

       uint32 CONFIG_PPROTSET1;

       uint32 CONFIG_PPROTSET2;

       uint32 CONFIG_PPROTSET3;

       uint32 CONFIG_PCSPWRDWNSET0;

       uint32 CONFIG_PCSPWRDWNSET1;

       uint32 CONFIG_PSPWRDWNSET0;

       uint32 CONFIG_PSPWRDWNSET1;

       uint32 CONFIG_PSPWRDWNSET2;

       uint32 CONFIG_PSPWRDWNSET3;

    }  l2l3_config_reg_t;

    Regards,

    QJ