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TMS570LS3137: What's the difference between the Cortex TCM error event counter via the PMU and the ESM memories errors?

jimj2713
Expert 2130 points
Part Number: TMS570LS3137

I am trying to monitor the count of ALL single-bit and multi-bit memory errors. The ARM core supports events-counters via the Performance Monitoring Unit, which can count parity and ECC errors. Also the TMS570LS3137-TCRAM register interface supports counts of single-bit errors via the RAMOCCUR register, plus the 3137 has ESM interrupts for single/multi-bit errors. 

Are these counts/events both potentially occurring on the same single error (if both configured), or does the PMU count different kinds of errors than RAMOCCUR/ESM do?

Maybe the question could be worded differently -- if properly configured, will the ESM interrupts occur for ALL single/multi-bit memory errors, or must I also use RAMOCCUR and/or the PMU for errors the ESM does not see?

Thanks,

Jim

  • 0
    TI__Guru 59540 points
    Hello Jim,

    The ESM is simply a notification module and the trigger of the ESM notification will come from the configuration within the ESRAM wrapper IP. i.e., the RAM threshold count will trigger the threshold interrupt when the RAMOCCUR count has matched the value configured as the threshold. It is important that the RAMOCCUR value be cleared to 0 before setting the threshold value since, if not, the synchronization between the two can be lost. The PMU would not be tied to the threshold function and is independent of the ESRAM wrapper logic.

    On a side note about counters being incremeneted, if a RAM location is read with a single bit error that is corrected, the corrected value is stored in a buffer within the Cortex-R4 CPU. This buffer is then accessed for any ongoing consecutive accesses so it will not cause an accumulation of single bit error correction counts. If however, there is a subsequent location accessed with a single bit correction, it will then be loaded to the buffer causing an increment. If the original location is accessed again, it is again loaded into the buffer and will cause the counter to increment.

    Double bit/uncorrectable errors will result in a CPU abort/ESM Group3 fault and are not tracked by the ESRAM wrapper parameters such as RAMOCCUR or the Threshold count. PMU events could still be incremented for these types of errors if configured to do so.