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TMS570LC4357: EMIF Interface with SDRAM and Asynchronous memory

Rajasekaran Mani
Prodigy 100 points
Part Number: TMS570LC4357

Hi All,

Existing Solution:

1)     Ethernet Receives data bytes and stores in SDRAM(EMIF Synchronous mode)

New design:

1)     Ethernet Receives data bytes and stores in SDRAM(EMIF Synchronous mode)

2)     100ms periodic application will request DMA to transfer data of 1000 bytes from SDRAM (EMIF Synchronous mode) to FPGA through EMIF Interface (Asynchronous mode).

Question:

As shown in the image, for transferring 1000 bytes we need 500 Asynchronous access cycles (EMIF 16 bit data).

Each Asynchronous cycle is of 40ns (Setup, Hold, Strobe, TA – 10ns each). So for 500 Asynchronous access cycles it takes 500 * 40ns = 2us.

As per Section 21.2.14.1 TMS570LC43x TRM

Asynchronous request < tRAS .

2us < 50ns --> Condition is not satisfied. Is this understanding correct?. Please share your view on this.

Thanks.

  • 0
    TI__Guru 59540 points
    Hello,

    I have forwarded your post to one of our experts on the EMIF IP. They should get back with you soon.
  • 0 in reply to Chuck Davenport
    Prodigy 100 points

    Hi Chuck Davenport,

    Thanks for your reply. I am waiting for your expert to reply on this question.

    Excerpts from TRM

    21.2.2 EMIF Requests
    Different sources within the SoC can make requests to the EMIF. These requests consist of accesses to
    SDRAM memory, asynchronous memory, and EMIF registers. The EMIF can process only one request at
    a time. Therefore a high performance crossbar switch exists within the SoC to provide prioritized requests
    from the different sources to the EMIF. The sources are:
    1. CPU
    2. DMA
    3. Other master peripherals
    If a request is submitted from two or more sources simultaneously, the crossbar switch will forward the
    highest priority request to the EMIF first. Upon completion of a request, the crossbar switch again
    evaluates the pending requests and forwards the highest priority pending request to the EMIF.

    Question:

    TRM Lists different request sources like CPU, DMA & other master peripherals.

    1) What is the priority order ? ( CPU --> DMA ---> Master perioherals ?)

    2) what are other master peripherals that can request EMIF?.

    Please give answers for the above two questions also.

  • 0 in reply to Rajasekaran Mani
    TI__Guru**** 186196 points

    Hello,

    1. The DMA and CPU has the same priority to access the slaves.The crossbar switch allows both the DMA (or other master peripherals) and the CPU core to access the bus slaves simultaneously, this speeds up execution time and performance. The DMA and the CPU cannot access the same peripheral at the same time. The round-robin arbitration scheme is used for scheduling.

    2. Flexray transfer unit is capable to access the external data memory. 

  • 0 in reply to QJ Wang
    Prodigy 100 points
    Hi Wang,
    Can you please answer me for the Query for the picture attached above.

    My Asynchronous request time:
    Read 1000 byte , Each access i can read 2 bytes.
    for one access i configured TA,setup, strobe and hold 1 cycle each . So 40ns
    Request time = 5000 * 40ns = 2us

    Synchronous memory configuration time
    tRAS = 50ns
    trefresh = 275us ,
    of the above two lower is 50ns

    As per Chapter 21.2.14.1 TMS570LC43x TRM

    Asynchronous request < tRAS or treferesh (which ever is lower of the two)
    2us < 50ns.

    With this setting both Sync and Async memory i cannot interface to work simultaneously.
    Is this understanding correct ?
  • 0 in reply to Rajasekaran Mani
    TI__Guru**** 186196 points

    Hello,

    Yes, your understanding is correct. tRAS used in the formula should be the maximum value which is defined in the SDRAM datasheet, typically it is 100us. The tRAS used in EMIF SDRAM timing register is the minimum value.