TMS570LC4357: TMS570LC4357 RTP does not appear to work in Trace Mode

Iceberg

Part Number: TMS570LC4357

Hello,

I was able to get RTP to work in Direct Data Mode by setting up the port to be 16 bits and assigning the GLBCTRL register to be as follows: I allow the clock to be free-running, and I disable the RTPENA pin so it can overflow. Writing to DDMW after this configuration (plus enabling the ports for 16 bits, no ENA pin) all pins output except for ENA.

/** - RTP Port output values */
rtpREG->PC3 = (uint32) 0U /* DATA[0] */
| (uint32)((uint32)0U << 1U) /* DATA[1] */
| (uint32)((uint32)0U << 2U) /* DATA[2] */
| (uint32)((uint32)0U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)0U << 5U) /* DATA[5] */
| (uint32)((uint32)0U << 6U) /* DATA[6] */
| (uint32)((uint32)0U << 7U) /* DATA[7] */
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)0U << 9U) /* DATA[9] */
| (uint32)((uint32)0U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)0U << 13U) /* DATA[13] */
| (uint32)((uint32)0U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)0U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port direction */
rtpREG->PC1 = (uint32) 1U /* DATA[0] */
| (uint32)((uint32)1U << 1U) /* DATA[1] */
| (uint32)((uint32)1U << 2U) /* DATA[2] */
| (uint32)((uint32)1U << 3U) /* DATA[3] */
| (uint32)((uint32)1U << 4U) /* DATA[4] */
| (uint32)((uint32)1U << 5U) /* DATA[5] */
| (uint32)((uint32)1U << 6U) /* DATA[6] */
| (uint32)((uint32)1U << 7U) /* DATA[7] */
| (uint32)((uint32)1U << 8U) /* DATA[8] */
| (uint32)((uint32)1U << 9U) /* DATA[9] */
| (uint32)((uint32)1U << 10U) /* DATA[10] */
| (uint32)((uint32)1U << 11U) /* DATA[11] */
| (uint32)((uint32)1U << 12U) /* DATA[12] */
| (uint32)((uint32)1U << 13U) /* DATA[13] */
| (uint32)((uint32)1U << 14U) /* DATA[14] */
| (uint32)((uint32)1U << 15U) /* DATA[15] */
| (uint32)((uint32)1U << 16U) /* RTP SYNC */
| (uint32)((uint32)1U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port open drain enable */
rtpREG->PC6 = (uint32) 0U /* DATA[0] */
| (uint32)((uint32)0U << 1U) /* DATA[1] */
| (uint32)((uint32)0U << 2U) /* DATA[2] */
| (uint32)((uint32)0U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)0U << 5U) /* DATA[5] */
| (uint32)((uint32)0U << 6U) /* DATA[6] */
| (uint32)((uint32)0U << 7U) /* DATA[7] */
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)0U << 9U) /* DATA[9] */
| (uint32)((uint32)0U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)0U << 13U) /* DATA[13] */
| (uint32)((uint32)0U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)0U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/** - RTP Port pullup / pulldown selection */
rtpREG->PC8 = (uint32) 1U /* DATA[0] */
| (uint32)((uint32)1U << 1U) /* DATA[1] */
| (uint32)((uint32)1U << 2U) /* DATA[2] */
| (uint32)((uint32)1U << 3U) /* DATA[3] */
| (uint32)((uint32)1U << 4U) /* DATA[4] */
| (uint32)((uint32)1U << 5U) /* DATA[5] */
| (uint32)((uint32)1U << 6U) /* DATA[6] */
| (uint32)((uint32)1U << 7U) /* DATA[7] */
| (uint32)((uint32)1U << 8U) /* DATA[8] */
| (uint32)((uint32)1U << 9U) /* DATA[9] */
| (uint32)((uint32)1U << 10U) /* DATA[10] */
| (uint32)((uint32)1U << 11U) /* DATA[11] */
| (uint32)((uint32)1U << 12U) /* DATA[12] */
| (uint32)((uint32)1U << 13U) /* DATA[13] */
| (uint32)((uint32)1U << 14U) /* DATA[14] */
| (uint32)((uint32)1U << 15U) /* DATA[15] */
| (uint32)((uint32)1U << 16U) /* RTP SYNC */
| (uint32)((uint32)1U << 17U) /* RTP CLK */
| (uint32)((uint32)1U << 18U); /* RTP ENA */

/** - RTP Port pullup / pulldown enable*/
rtpREG->PC7 = (uint32) 0U /* DATA[0] */
| (uint32)((uint32)0U << 1U) /* DATA[1] */
| (uint32)((uint32)0U << 2U) /* DATA[2] */
| (uint32)((uint32)0U << 3U) /* DATA[3] */
| (uint32)((uint32)0U << 4U) /* DATA[4] */
| (uint32)((uint32)0U << 5U) /* DATA[5] */
| (uint32)((uint32)0U << 6U) /* DATA[6] */
| (uint32)((uint32)0U << 7U) /* DATA[7] */
| (uint32)((uint32)0U << 8U) /* DATA[8] */
| (uint32)((uint32)0U << 9U) /* DATA[9] */
| (uint32)((uint32)0U << 10U) /* DATA[10] */
| (uint32)((uint32)0U << 11U) /* DATA[11] */
| (uint32)((uint32)0U << 12U) /* DATA[12] */
| (uint32)((uint32)0U << 13U) /* DATA[13] */
| (uint32)((uint32)0U << 14U) /* DATA[14] */
| (uint32)((uint32)0U << 15U) /* DATA[15] */
| (uint32)((uint32)0U << 16U) /* RTP SYNC */
| (uint32)((uint32)0U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

/* RTP set all pins to functional */
rtpREG->PC0 = (uint32) 1U /* DATA[0] */
| (uint32)((uint32)1U << 1U) /* DATA[1] */
| (uint32)((uint32)1U << 2U) /* DATA[2] */
| (uint32)((uint32)1U << 3U) /* DATA[3] */
| (uint32)((uint32)1U << 4U) /* DATA[4] */
| (uint32)((uint32)1U << 5U) /* DATA[5] */
| (uint32)((uint32)1U << 6U) /* DATA[6] */
| (uint32)((uint32)1U << 7U) /* DATA[7] */
| (uint32)((uint32)1U << 8U) /* DATA[8] */
| (uint32)((uint32)1U << 9U) /* DATA[9] */
| (uint32)((uint32)1U << 10U) /* DATA[10] */
| (uint32)((uint32)1U << 11U) /* DATA[11] */
| (uint32)((uint32)1U << 12U) /* DATA[12] */
| (uint32)((uint32)1U << 13U) /* DATA[13] */
| (uint32)((uint32)1U << 14U) /* DATA[14] */
| (uint32)((uint32)1U << 15U) /* DATA[15] */
| (uint32)((uint32)1U << 16U) /* RTP SYNC */
| (uint32)((uint32)1U << 17U) /* RTP CLK */
| (uint32)((uint32)0U << 18U); /* RTP ENA */

However, when I attempt to configure the port for Trace mode, and use a memory address of 0x08001000 and turn on tracing with the following code, when I attempt to write to an address in the 0x08001000 to 0x08001FFF range, I do not see the RTP Trace clock or any data come out.

//Set up Global tracing parameters:

//0 FIFO ram not mapped
//111 HCLK/8 (adjust for faster)
//00 reserved
//00 DDM_WIDTH not required for trace mode
//0 DDM_RW not needed for trace mode
//0 Trace Mode
//11 16 bit wide
//0 out of reset state
//1 clk free running (?)
//0 No Overflow Protection for now
//0 Trace inside of defined region
//1010 Enable Trace ("0xA")

Port config registers are same as before:

//map 1K from memory region 8001000, writes only

rtpREG->RAM1REG1 =0x13001000;

//set up trace for RAM block 1
rtpREG->TRENA |=0x01;

When I initialize rtp with rtpInit() and assign a pointer to memory for memory read/write:

uint32_t* MemRegion=(uint32_t *)0x08001000;

And I write to this memory region *MemRegion=0xAA55AA55 (or anywhere in the region from 0x08001000 to 0x08001FFF)

Shouldn't the trace port automatically make a copy of that region and send it to the FIFO for delivery out of the port?

Best,

Josh Karch

over 5 years ago

0 Iceberg over 5 years ago

Intellectual 565 points

Any updates on this? It's unclear to me if I'm doing something wrong here but data is not coming out once I switch configuration from Direct Data Mode to Trace Mode.

0 QJ Wang over 5 years ago in reply to Iceberg

TI__Guru**** 186256 points

Hello Iceberg,

One of our expert is working on RTP test and will come back to soon. Thanks

0 Sunil Oak over 5 years ago in reply to Iceberg

TI__Mastermind 49120 points

Josh,

I could not work on this issue today. Will try to get back to you by Monday.

Regards,

Sunil

0 Sunil Oak over 5 years ago in reply to Iceberg

TI__Mastermind 49120 points

Hi Josh,

Just a quick thought: the on-chip SRAM at address 0x08000000 is level-2 memory on the TMS570LC MCUs. Can you confirm whether the CPU cache is ON or OFF? If the CPU write happens to a memory defined as cacheable, the RAM may not "see" the access immediately if configured as a write-back cached region.

0 Iceberg over 5 years ago in reply to Sunil Oak

Intellectual 565 points

Sunil,

I can check that, but I will say that I make multiple writes to that memory in a loop and never ever see anything come out of the trace port.

Best,

Josh

0 Iceberg over 5 years ago in reply to Iceberg

Intellectual 565 points

Sunil,

Turning off the CPU cache seems to cause data to come out of the RTP now. This isn't really super-well documented. Page 2157 of the TRM states: "NOTE: This device implements Level 1 cache memory. Reading and writing from/to Level 2 RAMs
which is declared Cacheable can result in RAM traces that do not correspond to the
software's original intent. in this case absolutely nothing came out, which is probably good because incorrect tracing might have happened, but the documentation should reflect that CPU caching should be disabled to use RTP. Furthermore I wonder if RTP mode is actually of value for many because of disabled caching in the L2 RAM memory space. What also is strange is that multiple writes to the RAM memory space never activated the RTP, which means that disabling caching is a prerequisite for using RTP in this memory region.

0 Sunil Oak over 5 years ago in reply to Iceberg

TI__Mastermind 49120 points

Josh,

You can configure the memory region as write-through cacheable and see better results. The issue would still remain if you tried to trace reads from RAM.

Regards,
Sunil

0 Iceberg over 5 years ago in reply to Sunil Oak

Intellectual 565 points

Sunil, sounds good, looks like the caching prevented operation, so Thank you for suggesting that fix.
Best
Josh Karch

Arm-based microcontrollers

Arm-based microcontrollers forum

TMS570LC4357: TMS570LC4357 RTP does not appear to work in Trace Mode