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TMS570LS3137: about tC2TDELAY time

Part Number: TMS570LS3137

Hi Wang-san,

When SPIENA is enabled, tC2TDELAY is out of the range specified in the data sheet.

When checking "Wait for enable" as below, tC2TDELAY can not be within the range defined by DS.

When "Wait for enable" is not checked, tC2TDELAY falls within the range specified by DS.

Why is this? When checking A, does not this rule apply?

Best regards,

Sasaki

  • Hello Sasaki,

    When WAITENA is set, the SPI doesn't transfer data until the ENA signal becomes LOW. 

    The actual delay between CS active (falling edge) to ENA active (falling edge) is determined by the salve. If the ENA is not pulled low before the timeout (C2EDELAY), the master aborts the transfer and sets the timeout error flag. 

    What is C2EDELAY in your setting? TC2TDELAY should not include the ENA delay.

  • Hi Wang-san,

    Thank you for your support!

    What is C2EDELAY in your setting? 

    My setting is below.

    TC2TDELAY should not include the ENA delay.

    I understood it! The waveform is correct unless ENA delay is included.

    Best regards,

    Sasaki