Other Parts Discussed in Thread: TMS570LS3137-EP
Hello,
We are currently using your following component in our development: TMS570LC4357.
The support requested is about the SSWF021#45 Errata (PLL fails to start) and especially the workaround proposed through the application note 'spna233a'.
1. The proposal in this application note is to use the DCC module in Single Shot Mode.
However, the suggested workaround for DCC#24 errata sheet (errata about the usage of DCC module in single shot mode) is not implemented in the workaround for the SSWF021#45 issue.
Therefore we suggest to use the DCC module in Continuous mode instead for the SSWF021#45 workaround.
-> First of all, is this acceptable for you and is it compatible with the application note 'spna233a' ?
2. Below is a brief description of the foreseen method to use the DCC in Continuous mode for the SSWF021#45 workaround.
a.
We choose to use in the DCC1 module OSCIN (external oscillator) as clock source to compare the main PLL output (also from OSCIN).
b.
To use the continuous mode, we have to make a delay in order to wait that the DCC module performs one or several laps but we do not have PLL locked at this moment.
So, at this step of configuration, for us, the simplest solution is to use the internal timer of ARM core (See Cortex-R5 reference manual (revision r1p2) chapter "6.3.7 c9, Cycle Count Register").
By default, the core and its timer are cadenced by the internal oscillator.
We propose that the core works from OSCIN (Benefits: delay and DCC module are from the same clock source (OSCIN)).
c.
Before plugging OSCIN on the core, we propose to make sure that OSCIN works (not freezed).
The OSCFAIL status bit of GLBSTAT register is useful in this case (see 'spnu563a' reference manual: Chapter "14.4 Low Power Oscillator and Clock Detect (LPOCLKDET)" : The LPOCLKDET module generates the OSCFAIL flag in the Global Status Register (GLBSTAT)).
Once we know that OSCIN works, we can use it for the internal clock generation: OSCIN for the DCC module and for the core.
d.
DCC module in continuous mode:
- We configure DCC in continuous mode, OSCIN as clock source for DCC1 counter0 and main PLL as clock source for DCC1 counter1.
- We perform a delay with two or three DCC loops.
- At the end of the loops, we clear the DCC status, in case where the starting will cause a wrong error.
- Then, we wait once again two or three DCC loops.
- We check the DCC status (via error flag ERR bit in DCCSTAT register).
Note1: The delay is equal to the initial value of DCC counters.
Note2: When the initialisation is over (PLL started and locked), we stop the DCC module.
-> Could tell us more information about this request and our porposal?
Best regards,
Christopher TRITANT
