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TMS570LS0432: Enable PBIST clocks and ROM clock for PBIST self-test

Expert 1995 points
Part Number: TMS570LS0432

Hello all,

Is there some special reason why in the pbistSelfCheck() function the PBIST clocks and ROM clock are re-enabled by writing 0x3 on the PACT register (see the code below)? Actually 0x01 should be sufficient.

/* Enable PBIST clocks and ROM clock */
    pbistREG->PACT = 0x3U;

Also the PBIST Memory Self-Test Flow Diagram at the stage says PACT = 0x3U.

UPDATE: I have found the PBIST patent describing also the ROM clock register PACT[1], I checked some revision history of other TMS570 and this has been removed from the documentation but the code remains the same. Can anybody tell me if it is more correct to write 3h or 1h into that register ? Thanks.