We are using the EMIF on the TMS570LC4357 (with ARM® Cortex® - R5F). According to the Datasheet (below), the EMIF is BE8 and the device is BE32. A description is provided in the Datasheet to wire the bus to perform the format conversion.
We have a device containing a 32-bit read-only register at 0x60000024 set to 0x18101207 connected to the EMIF using the BE8/BE32 wiring given in the datasheet. We have observed that reading address offset 0x4 and 0x6 as 16-bit (Half-Word) reads the data appears correct however, when read as a 32-bit word at offset 0x4, the Half-Words are swapped. Here are the results:
Read ADDR=0x60000024, SIZE=16; return value = 0x1207 <-- expected value
Read ADDR=0x60000026, SIZE=16; return value = 0x1810 <-- expected value
Read ADDR=0x60000024, SIZE=32; return value = 0x12071810 <-- unexpected value (expected 0x18101207)
Can you explain this Half-Word swap behavior?
The Coretex-R5 manual indicates it does not support BE32 but the TMS570 Datasheet indicates this device is BE32. Can you explain this disagreement?
TMS570LC4357 datasheet (SPNS195C –FEBRUARY 2014–REVISED JUNE 2016):
The EMIF is inherently BE8, or byte invariant big endian. This device is BE32, or word invariant big endian. There is no difference when interfacing to RAM or using an 8-bit wide data bus. However, there is an impact when reading from external ROMs or interfacing to hardware registers with a 16-bit wide data bus. The EMIF can be made BE32 by connecting EMIF_DATA[7:0] to the ROM or ASIC DATA[15:8] and EMIF_DATA[15:8] to the ROM or ASIC DATA[7:0].
Alternatively, the code stored in the ROM can be linked as -be8 instead of -be32.
For a 32-bit access on the 16-bit EMIF interface, the lower 16-bits (the EMIF_BA[1] will be low) will be put out first followed by the upper 16-bits (EMIF_BA[1] will be high).
Coretex-R5 Technical Reference Manual (ARM DDI 0460D ID092411):
The processor supports byte-invariant big-endianness BE-8 and little-endianness LE. The processor does not support word-invariant big-endianness BE-32. Bit [7] of c1, Control Register is always 0.
