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TMS570LC4357: In which cases the Cortex-R5 core detects an AXI Decode error?

Etienne Alepins
Intellectual 775 points
Part Number: TMS570LC4357

Hi,

ARM Cortex-R5F TRM document says in §8.3. "Fault handling" of level 1 interface that for both instruction fetches and data accesses, the following errors can occur:

• External AXI slave error (SLVERR)
• External AXI decode error (DECERR)

The DFSR/IFSR register has a field "SD" which tells if the Abort was of type SLVERR or DECERR. From my understanding, a slave error occurs when one peripheral (e.g. L2RAM or Flash) returns an error upon a memory access, for example upon an ECC error in RAM during a read-modify-write. The question is: what kinds of actions in the TMS570LC can generate a DECERR? I couldn't find any... Is the AXI master interconnect including some checks in its decode logic that can return an error to the core? For example when accessing an empty space in the memory map? (e.g. 0x2000_0000)

Thanks,

Etienne

  • 0
    TI__Mastermind 49120 points

    Hi Etienne,

    I ran a quick check on the error status and address registers in the CPU. The bit 12 (SD) of the fault status register always reads as set, indicating a Slave Error even if I access a memory location that is not valid. This is because there is a "default" slave that is addressed when the access goes to any invalid address, and this default slave returns an error response that is captured as a "Slave Error".

    Regards,
    Sunil

  • 0 in reply to Sunil Oak
    Intellectual 775 points
    Hmm... That would mean that all external aborts are DECERR? Then, I reverse the question: is it possible to generate a SLVERR?
    I was looking at an answer replying on the internal schematics of the ARM core integration in your SoC rather than an experimental answer...
    Which kind of manipulation did you do to obtain your abort? I suspect it was a Prefetch Abort. I am wondering if you'd get the same SD value with a Data Abort.
    Thanks.
    Etienne
  • 0 in reply to Etienne Alepins
    TI__Mastermind 49120 points
    Etienne,

    SD = 1 means that it is detected as a "Slave Error" and not a decode error. I caused a data abort by reading from an invalid address. As I stated before, these accesses "fall through" to the default slave, which sends an error response back to the CPU causing the abort.

    Regards,
    Sunil