TMS570LC4357: FlexRay integrating node into existing network

Hello,

It seems that indeed the problem was more than likely the poorly configured PLL2. Now I have managed to integrate the node into the network and I am able to see in the new data registers that in the buffer that I configured I have some data.

However, I still have some questions.

1. In the example code, even when configuring a buffer as an RX one, after setting all the parameters, there is still a call to the Fr_TransmitTxLPdu, and I do not see why this is important, and how it affects everything.

	// buffer #10
	Fr_LPduPtr->fid  = 10;     // frame ID
	Fr_LPduPtr->dp   = 0x240; // Pointer to start of data in message RAM
	Fr_LPduPtr->cfg  = 0;    // RX frame
	Fr_LPduPtr->crc  = 0;

	Fr_LSduPtr->ibrh = 10;  // input buffer number

	Fr_PrepareLPdu(Fray_PST, Fr_LPduPtr);
	Fr_TransmitTxLPdu(Fray_PST, Fr_LSduPtr);

This is a code snippet taken from the flexray example.

2. How does the transfer between the message buffer data and output buffer registers happen?

At the moment, I have tried to see whether the data received is changing, but in the output buffer registers ( RDDS ), there are only zeroes. I have changed the configuration from the demo to match what I have changed, since I only set one message buffer, the first one, as a receive message buffer.

      read_buffer->obrs=1;  // output buffer number
	  read_buffer->rdss=1;  // read data section
	  read_buffer->rhss=0;  // read header section
      // Transfer message buffer 1 data to output buffer registers
      Fr_ReceiveRxLPdu(Fray_PST, read_buffer);
      if (Fray_PST->RDDS[1] != 0x87654321) error++;

3. In the example code provided when configuring the flexray module, the following lines are used to initialize the interrupts:

	// Initialize Interrupts
	Fray_PST->EIR_UN.EIR_UL       = 0xFFFFFFFF; // Clear Error Int.
	Fray_PST->SIR_UN.SIR_UL       = 0xFFFFFFFF; // Clear Status Int.
	Fray_PST->SILS_UN.SILS_UL     = 0x00000000; // all Status Int. to eray_int0
	Fray_PST->SIER_UN.SIER_UL     = 0xFFFFFFFF; // Disable all Status Int.
	Fray_PST->SIES_UN.SIES_UL     = 0x00000004; // Enable CYCSE Int.
	Fray_PST->ILE_UN.ILE_UL       = 0x00000002; // enable eray_int1

It can be seen that the register SILS_UN is set so that all the status interrupts are assigned to interrupt line eray_int0. However, when setting the ILE_UN register, by placing the value 0x00000002 just the eray_int1 interrupt line is enabled. My question is: shouldn't either both interrupt lines be enabled, or at least eray_int0, since all the status interrupts are assigned to it?

Thank you,

Adrian.