TMS570LS1224: MibSpi Enable Pin during slave operation

Hello,
For SPIENA to go low in 5 pin mode, two conditions must be true. Slave must be selected by Master (CS is low) and new data has to be written to
the slave shift register (SPIDAT0/SPIDAT1). In attached diagram, SPIENA goes low before Slave is selected (CS low) . This makes me think that SPIENA line is not driven by Slave.

Best regards,
Miro

Hello Miroslav,

Thank you for your reply. 
I understood regarding the 5 pin mode. 

In the diagram the SPIENA is being driven by the Slave and the rest of the signals by the master. It is in 4 pin mode. The master would wait for the slave to pull SPIENA low and then send the message. But when will the SPIENA will be pulled back to high by the slave? (As you can see in the picture, it is not being pulled back high). 

Regards

Varun

Hello Varun,

The Slave needs to deassert the SPIENA pin after the last bit is received.

It is not going high. Just configuring it as functional and output in Halcogen is enough is what I am assuming? I called the set data and transfer function but still it is not being pulled high after the transfer. Can you replicate my issue on your end ? Am I missing something?

Regards
Varun

Hello Wang, Miroslav

After inspection I found out that TGENA bit in TGCTRL register is not being cleared after the transmission has taken place. I have configured the trigger event to be always and trigger source is disabled. So I am initiating the transfer by setting TGENA bit. I also set OneShot transfer. Do you know why TGENA is not being cleared? Any thoughts? Right now I am waiting for the transmission to end and then clearing the TGENA bit on my own. 

Regards
Varun

Hi Varun,

Can I have your code to try on my bench?

Hello Varun,
I am closing this thread because there is no activity for a long time. If you did not solve your problem please, write bellow or open new thread.

Best regards,
Miro

Hi Wang/Miroslav,

I am sorry I was away from this issue for sometime now and I never got a chance to get back. I have attached my code. Can you please try on your bench and let know know. The issue still remains.  Again I apologize for the delay. I tried attaching my Halcogen file but it did not take it.3515.sys_main.c

Thanks!

Varun

Hello Varun,
In Slave mode TGENA bit will remain set!

Best regards,
Miro

Hi Miro,
Thanks, my question is more why ENA pin is not going high? In the picture I added in first question, ENA pin( the first signal) is going low before transmission and it is not going to high after the SPI is completed.

Thanks
Varun

Hello,
I'll do some tests on my desk.

Best regards,
Miro

Hello Varun,
Sorry for the delay.
I have just made a test with TMS570LS3137 HDK as Master and TMS570LS1224 LaunchPad as Slave. Everything work as expected.
According to TRM CS is driven from the Master before ENA pin is driven from the slave. In picture posted above CS goes low after ENA. Please check whether ENA pin is driven from Slave (not from some other part of your HW setup).

Best regards,
Miro

Hi Miroslav,

I am sorry I might have confused you in my question by including the picture. I am dealing without CS. There is only one master and one slave.

In the document TMS570LS12x technical reference manual, in MibSpi, there is Operation with SPIENA section which does not deal with CS as shown in the diagram in the manual. It is 4 way handshake with CLK, MISO,MOSI, SPIENA signals that I am trying. As you can see there is no CS, so only SPIENABLE goes low before the transmission it should go high after transmission. Please check it on your bench and let me know and thanks for your effort . 

Regards

Varun

Hello Varun,

My apologies for delayed response.

In slave mode, the SPI module will drive only the SPISOMI and SPIENA pins. All other pins are inputs to it. The RX data on the SPISIMO pin will be registered with respect to the SPICLK pin. The Slave will use the SPICS pin to drive out the SPIENA pin if both are functional. If 4-pin with SPIENA is configured, then the Slave will drive out an active-low signal on the SPIENA pin when new data is written to the TX Shift Register. Irrespective of 4-pin with SPIENA or 5-pin configuration, the Slave will deassert the SPIENA pin after the last bit is received. If ENABLE_HIGHZ (SPIINT0.24) bit is 0, the de-asserted value of the SPIENA pin will be 1. Otherwise, it will depend upon the internal pull up or pull down resistor.