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  • TI Thinks Resolved

TMS570LS1227: Problem with het uart

Intellectual 320 points

Replies: 6

Views: 191

Part Number: TMS570LS1227

Hi,

we have another problem here with the uart running in the het.   When receiving blocks of data back to back it seems to be losing synchronisation after a while.   So in a block of 256 bytes after about 150ish bytes there are only incorrect bytes being received.   One byte is always missing.

So can somebody confirm / deny if the ti het uart emulation can operate at 57600baud with a VCLK2 of 48MHz and an LRPFC of 64?   I get a figure of 57692baud so in theory there should not be any characters being lost.

Regards,

  • Guru 63890 points

    Hello,

    Is there data missing at 115200 baudrate with VCLK2=96MHz, LRPFC=64? Did you make any modification to the HET source code?

    Thanks and Regards,
    QJ Wang

  • In reply to QJ Wang:

    Hi QJ,

    I don't know if it works at 96MHz.  This is no option for us due to the poor ti clock divider / select design.   Scaling everything up by 2 should not make a difference.

    I added one line of comment regarding the 57600 at 48MHz VCLK2, so yes, I did change the source code.

    Regards,

  • Guru 63890 points

    In reply to hagen wegner:

    Hi Hagen,

    HALCoGen is nice tool to configure the PLL and VCLK:

    Thanks and Regards,
    QJ Wang

  • Guru 63890 points

    In reply to QJ Wang:

    Thanks and Regards,
    QJ Wang

  • In reply to QJ Wang:

    Hi QJ,

    > HALCoGen is nice tool to configure the PLL and VCLK:

    Oh really???   I will tell you now what I think of your Halcogen stuff. 

    In the past few years semiconductor companies are trying to tie you into their hardware by providing all those fancy graphical tools, IDEs, hardware drivers, "middleware" and so on.   Once you started using even their hardware drivers you are pretty much tied to that manufacturer.   Not a hope moving onto another manufacturer.   Mission accomplished.

    ti went even a step further: they don't provide hardware drivers, they provide what they call "halcogen", a mouse click tool where you can configure an IC and hey, presto, out falls thousands of lines of code with even more magic numbers in it and the engineer saved months of hard work.   Absolutely great, isn't it?

    Well I tell you now what I think of halcogen: we had a prototype running on an eval board; all the code generated with halcogen.  Then we had to change to another processor because the peripherals were even worse than on the one we are using now.  Do you have an idea how long it took us to replicate all those thousands of mouse clicks until originally working software was running again?    Moving from a TMS570 to another TMS570?

    Halcogen is a deeply flawed concept: generating magic numbers through mouse clicks.   The former does do allow you to move even to another ti processor and the latter is highly inefficient and prevents automation of code generation for the customer.   But of course it is great for ti, it even covers up all the errata traps that the software designer would have stepped into otherwise.   You can even flog faulty hardware with only a few people noticing.

    A good concept would have been to provide generic processor independent hardware driver functions which you can call from your own (existing) software possibly with an intermediate layer to get rid of that obnoxious microsoft style camelcase (no surprise microsoft never produced any good software).  But no, very basic functions are missing: how do I set my SPI format?   How do I set my processor and peripheral clock rates?  And so on. and so on.

    And what I was referring to with poor design is the processors themselves.   Maybe ti should have talked to experienced system designers before they created silicon.   Your clock module up there is good but the problem lies further down the line:

    Eight peripherals dangling of one clock?  Two of them the ADCs?   Two poky uarts on an IC with 1/2 squaremile of silicon that costs $20 (and ti using uarts on ics we are interfacing to)?   Loads of power pins and fixed analogue inputs reducing the usable pin count effectively to half?

    We were forced to use the low end timer then for a soft uart with ti supplied software which worked fine until we discovered one day before the prototypes had to be shipped to the customer that the thing was losing bytes when being hammered with a continuous data stream.   We worked around that by introducing delays on the computer side and I posted a question here where the only suggestions so far is to increase the clock speed on both sides and how great halcogen is.

    I can assure you, if it would not be for my customer insisting on ti we would have eliminated ti processors from this design a long time ago.  But after all the problems we had with the silicon and the software and the tools I think chances are good that I can still convince them to throw out ti for the production models.   I should have stuck to what a software Guru in IBM advised a long time ago: "If you are having problems at the beginning, walk away from it, you will find way more and serious problems further down the line".

    From our side this matter is closed.    Not resolved but closed.

    Have a nice day,

    p.s.: have you corrected the (in my humble opinion serious) fault in your boot loader f021 ram copy function yet?

  • In reply to hagen wegner:

    Hi Hagen

    Thank you for the candid feedback on Halcogen and its use-ability and the inputs on clocking architecture. Acknowledged ! 

    Halcogen as a concept was good to get customers started quickly and also help with any design/documentation quirks, especially on devices intended to be used in functional safety application  - but I can see your point on "mouse clicks" and need for generic hardware drivers with hardware abstraction layers.  

    We may also have not make significant investments to make the Halcogen product better over time  but while I understand your perspective, some customers do love the simplicity of this but probably over estimate what ease of use it is supposed to bring and as you have noted in several of your posts - it does not take away the diligence required on the customer side to make sure that the software works as expected to help achieve their application and functional safety goals for their products (no short cuts there) 

    FWIW for users with thought process similar to you - our newer more complex SoC  devices in Sitara family like AM65x which are also designed to help customer achieve their functional safety goals for their applications with hardware and software support (Safety diagnostic library , CSP etc) 

    I am disheartened to see the occasional colorful language in your posts - but perhaps it is more out of frustration. I am happy to get on a call with you to take any "constructive" feedback - although it may not help you with your current situation - it may help us add more feedback into future offerings.

    Good luck.

    Regards

    Mukul 

    (will mark the post resolved - as there is no "close" button)

    Do note that we have noted your feedback on f021 too, no plans to update that software offering, but will be happy to add anything to upcoming FAQs, so that users are aware of it. 

    Thanks

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