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TMS570LC4357: Questions about management of RXnHDP registers of EMAC in TMS570LC43x

ecarre
Prodigy 100 points
Part Number: TMS570LC4357

Hello,

I have some questions about management of RXnHDP registers of EMAC in TMS570LC43x microcontroller regarding our software design.

The Technical Reference Manual (SPNU563) provides the following statements:

  • 32.2.6.2 Transmit and Receive Descriptor Queues (page 1751)
    "The HDP must never be written to while a list is active."
  • RXnHDP registers (page 1849)
    "Writing to these locations when they are nonzero is an error (except at reset)."

I understand that until a RX buffer descriptors list is active, the user shall not write the associated RXnHDP register.

The software design is based on 2 RX buffer descriptors lists used as flip/flop. When EMAC fills a list, CPU processes the other list. Then at a fixed period, the lists are exchanged and a new cycle is executed. It is ensured by design that no Ethernet frame will be received during the flip/flop processing.

Here are the questions:

  • Because of lists are oversized with margins, the EMAC list will be still active at the beginning of the new cycle. If I refer to the technical manual I could not write the new head list pointer in the corresponding HDP. However is it correct to disable the receive (RXCONTROL.RX at 0), perform the write on RXnHDP, and enable the receive (RXCONTROL.RX at 1).
  • In case of reception of an Ethernet frame during the receive disable (not possible by design but I ask the question for robustness and safety purposes), I understand the consequence should be the set of teardown complete flag (TDOWNCMPLT) in the buffer descriptor which was currently filled by the EMAC. The EMAC still stays in a valid state.

Regards

  • 0
    TI__Guru* 95265 points

    Hi,

    I looked at the TMS570LC43x Ethernet driver, the code only uses 1 Tx and 1 Rx DMA channel, that is channel 0. The RXCONTROL.RXEN is enabled once, we didn't toggle between the enable and disable. I am looking the information how do you flip between two RX DMA channels.   

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    Hi,

    Sorry for the late response, I am still looking for the information.

    Regards, Eric

  • 0 in reply to lding
    TI__Guru* 95265 points

    Hi,

    Through reading the tms570lc4357 document (SPNU563A): 

    The host commands a receive channel teardown by writing the channel number to the receive teardown
    register (RXTEARDOWN). When a teardown command is issued to an enabled receive channel, the
    following occurs:
    • Any current frame in reception completes normally.
    • The TDOWNCMPLT flag is set in the next buffer descriptor in the chain, if there is one.
    • The channel head descriptor pointer is cleared to 0.
    • A receive interrupt for the channel is issued to the host.
    • The corresponding receive channel n completion pointer register (RXnCP) contains the value FFFF
    FFCh.
    Channel teardown may be commanded on any channel at any time. The host is informed of the teardown
    completion by the set teardown complete (TDOWNCMPLT) buffer descriptor bit. The EMAC does not
    clear any channel enables due to a teardown command. A teardown command to an inactive channel
    issues an interrupt that software should acknowledge with an FFFF FFFCh acknowledge value to RXnCP
    (note that there is no buffer descriptor in this case). Software may read RXnCP to determine if the
    interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a
    teardown command.

    TDOWNCMPLT bit is set by the EMAC, not the application. 

    In your case, I would suggest still use one Rx DMA channel without flipping between twos. When you have multiple packet descriptors, you can add them by:

    To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the
    software application simply writes the pointer to the descriptor or first descriptor of a list to the
    corresponding HDP register. Note that the last descriptor in the list must have its “next” pointer cleared to
    0. This is the only way the EMAC has of detecting the end of the list. Therefore, in the case where only a
    single descriptor is added, its “next descriptor” pointer must be initialized to 0.
    The HDP must never be written to while a list is active. To add additional descriptors to a descriptor list
    already owned by the EMAC, the NULL “next” pointer of the last descriptor of the previous list is patched
    with a pointer to the first descriptor of the new list. The list of new descriptors to be appended to the
    existing list must itself be NULL terminated before the pointer patch is performed.

    Regards, Eric

  • 0 in reply to lding
    Prodigy 100 points

    Hello,


    Thanks for your feedback. Your answer is exhaustive.


    I understand I can stop the EMAC with the “teardown” function but you (TI) recommends to work with a channel which is always enable and to manage the list.

    Thank you.

    Best regards,