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Part Number: TMS570LS3137
I'm trying to configure MibSPI that works with DMA, enabling internal loopback to simplify debugging. I modified HALCoGen example 'example_mibspiDma.c' by setting MibSPI5, I also added a DMA channel (DMA_CH1) for SPI reception, so that the message being received is copied directly from the DMA into the RX_DATA buffer to reduce CPU overhead, but it doesn't work.
The transmission buffer from TX_DATA to mibspiRAM5->tx (by DMA_CH0) is correctly, but the reception is wrong, only the first valute (uint16) is compiled from mibspiRAM5->rx to RX_DATA buffer.
The configuring DMA control packet stack for Tx and Rx seems correct, I also tried to enable interrupt for debugging and it works correctly.
Below I attach the sources of the test project and a screenshot where I highlighted the RX_DATA buffer.
Thanks, Davide Battistoli
RXDMA_MAPx: is the number of the physical DMA request line connected to RX path of MibSPI DMA channel--> the number in blue circle in the table 6-41 below
TXDMA_MAPx: is the number of the physical DMA request line connected to TX path of MibSPI DMA channel--> the number in blue circle in the table 6-41 below
The DMA module on TMS570LC43x has 48 hardware DMA requests (last column in Table 6-41 above)
In DMA configuration, please assign the DMA request to the DMA channel 0 and channel 1, for example
dmaReqAssign(DMA_CH0, DMA_REQ6); //DMA HW request line 6 -- RX (last col, Table 6-41)
dmaReqAssign(DMA_CH1, DMA_REQ7); //DMA HW request line 7 -- RX (last col, Table 6-41)
Please use TXDMA_MAPx, RXDMA_MAPx in mibspiDmaConfig() function: for example:
mibspiDmaConfig(mibspiREG5, TG0, 3, 2);
Thanks and Regards,QJ Wang
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In reply to QJ Wang:
Hi QJ Wang,
I'm using TMS570LS3137 and no TMS570LC43x , but I think the DMA module works in the same way with MibSPI.
I modify my test program as you told me, but the same RX_DATA buffer receives only the first value.
Also, it is not clear to me what is the tx and rx channel of the MibSPI5 (reading the user manual), the value 2 or 3? Or is it indifferent ? In the case of using the SPI in buffer mode, because in the standard SPI mode it is not true, as reported in the manual.
Could there be something else wrong with the test project?
I attach the modified code sources.
Thank you for your support
In reply to Davide Battistoli:
mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)
3 (txChannel) is TXDMA_MAPx
2 (rxChannel) is RXDMA_MAPx
Each MibSPI has 16 DMA request lines, you can choose any one for your TX and RX. The number of this DMA request line is the number in the bracket following MibSPI5[x].
If you chose MibSPI5 for TX, you have to assign the DMAREQ (last column) to this DMA channel (DMA_CH0 is used in your code)
If you choose MibSPI5 for RX, you must assign the DMAREQ to this DMA channel (DMA_CH1 is used in your example)
I draw a simple diagram to show those mappings:
Hello QJ,I understand how to map DMA channels, the correct DMA configuration are: dmaReqAssign(DMA_CH0, DMA_REQ6);dmaReqAssign(DMA_CH1, DMA_REQ7);mibspiDmaConfig(mibspiREG5, TG_0, 2, 3);
dmaReqAssign(DMA_CH0, DMA_REQ7);dmaReqAssign(DMA_CH1, DMA_REQ6);mibspiDmaConfig(mibspiREG5, TG_0, 3, 2);
by configuring the Contro packet in the following way:
txDmaConfigCtrlPacket((uint32)(&TX_DATA), (INT32U)(&(mibSpiRAM->tx.data)), 16); // size TX_DATA /* - setting dma control packets */setCtrlPacket(DMA_CH0, g_dmaCTRLPKT);rxDmaConfigCtrlPacket((uint32)(&(mibSpiRAM->rx.data)), (uint32)(&RX_DATA), 16); // size RX_DATA/* - setting dma control packets */setCtrlPacket(DMA_CH1, g_dmaCTRLPKT);
and another important thing, is that I didn't set correctly the 'bufid' value into mibspiDmaConfig() function
uint32 bufid = (16-1); // buffer size - 1
In addition, I am using FTC interrupt to capture the end of the last frame.
Now, the DMA works correctly with MibSPI5 using Buffer mode. I'm using an Evulation board where 4 ADCs are connected on the MibSPI5, periodically every 250 usec (managed with interrupt timer) I receive the data from the 4 ADCs correctly.
I have greatly reduced CPU overhead.
Thanks and Regards,Davide
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