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TMS570LS0914: ECC Memory scrubbing

Part Number: TMS570LS0914
Other Parts Discussed in Thread: TMS570LC4357

In the question that this one refers to, there is an answer that asks me to look at the MSE bit in the RAMCTRL register.  I infer that when this is set, if a single bit error is corrected, the corrected version is written back to the memory.  But I do not see that bit in RAMCTRL in my MTR.  Does this only exist in some TMS570 processors?  Does that mean that in my processor, if there is a corrected error, I should write it back myself to reduce the probability of a double-bit error?

  • Hello Burns,

    Memory Scrubbing Enable (MSE) bit is only for L2RAMW module on TMS570LC4357 and RM57Lx devices. For LS0914 device, the 1-bit ECC error will be corrected and the corrected data will be written back to RAM.

  • Oh, thank you.  So just to confirm, then, I do not have to manually write back the memory where a single-bit error was corrected (I've seen it differently in other places).  But I assume that I can still get a group 1 interrupt and log the address out of the RAMSERRADDR address.  And I assume I then have to clear the bit in the RAMERRSTATUS register in order to allow the next one to be logged.  True?

    Is it also fair to assume that a single bit correction in flash is NOT written back?  

  • Hello,

    Yes, the flag is set when the error threshold is reached. In order to store the next single bit error address, the SERR error status bit in the RAMERRSTATUS register needs to be write-clear.

    You are write. The corrected flash data is not written back to the flash.

  • Very good.  Thanks, QJ.