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TMS570LS0432: This CPU clock Test

Part Number: TMS570LS0432

Hello

Team 

I use the cpu TMS570LS0432. 

1.Dose this cpu have the clock test function?

2.How do test the tms570ls0432 cpu clock?

  I enable the DDC driver in the driver enable of HCG.this select  .what does this mean .

  • Hello Whong,

    The device has a built-in clock detection circuit which is used to monitor the oscillator.

    While power-on reset is asserted (low), the oscillator and low power oscillator (LPO) are enabled and start-up by default. After power-on reset is released to a high level, the clock detect circuit (CLKDET) begins to monitor the oscillator. If the oscillator is within a valid range, the oscillator becomes the default clock for the device as it exits reset; if the oscillator is not within a valid range, the clock detect selects the high-frequency low power oscillator as the default clock for the device.

    To monitor PLL clock, you can use DCC in your application: PLL output clock as one clock source (#1), and main oscillator as the #0 clock source. Please refer to the DCC chapter of TRM.

    check_frequency(uint32 cnt1_clksrc) function in errata_SSWF021_45.c uses DCC to checking PLL frequency. Please use this function as a reference.

  • Hello

     Thank you

    1.If I want to do clock monitoring.Execute this function“ check_frequency”periodically?Judge the result by return value?

    And How to enable DCC function in my program?

    2.If I don’t do clock monitoring, how can I convince the certification company that CPU hardware have reliable clock

  • Hello Whong,

    1. You can check the PLL clock using either DCC or ECLK output. The DCC can be used in two different operating conditions: Continuous Monitoring Mode and Single-Shot Measurement Mode. 

    2. The DCC diagnostic is not enabled by default and must be enabled via software. The DCC contains two counters – counter0 and counter1, which are driven by two clocks: clock0 and clock1. You need to programs the seed values for both counters, and configure the tolerance window time (valid counter for clock0). The Counter0 and counter1 start counting simultaneously. The DCC is enabled by programming DCC Control Register (DCCGCTRL).

    3. This device also supports other methods to chekc the clocks: oscillator detection, PLL slip check, watchdog