Other Parts Discussed in Thread: HALCOGEN,
Hello, I am looking for reference on how to perform PBIST self test. I see in technical reference manual, there is a statement which says 'Supports testing of PBIST ROM itself as well'. I wanted to perform PBIST self test and I am following the below steps. Always the test fails, need your support and guidance.
// Step 1:
// Disable PBIST internal clocks.
pbist_regs[PACT] = 0x0UL;
// Step 2:
// ROM clock source is GCLK1 divided by 4. PBIST will reset for 64 VBUS cycles
// Maximum PBIST ROM_CLK frequency supported is 82.5MHz.
// Memory self-test controller is disabled
sys_regs[MSTGCR] &= 0xFFFFFCF0UL;
sys_regs[MSTGCR] |= 0x00000205UL;
// Step 3:
// Global memory hardware initialization is disabled
sys_regs[MINITGCR] = 0x5UL;
// Step 4:
// Memory self-test controller is enabled
sys_regs[MSTGCR] &= 0xFFFFFFF0UL;
sys_regs[MSTGCR] |= 0xAUL;
// Step 5:
// Memory self-test run complete status: Memory self-test is not completed
sys_regs[MSTCGSTAT] = 0x1UL;
// Step 6:
// PBIST controller is enabled
sys_regs[MSINENA] = 0x1UL;
// Step 7:
// Wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio
#define VBUS_CLK_CYCLES 64U
for (Uint32 index = 0UL; index < (VBUS_CLK_CYCLES + (VBUS_CLK_CYCLES * 1u)); index++);
// Step 8:
// Enable PBIST internal clocks.
pbist_regs[PACT] = 0x1UL;
// Step 9:
// CPU control of PBIST, setting this bit allows the host processor to
// configure the PBIST controller registers
pbist_regs[DLR] = 0x10UL;
// Step 10:
// TODO: Custom always fail algorithm, this will not use the ROM and just set a fail
// Ram Group Select: 0
// Return Data Select: 0
// Data Width Register: 2
// Sense Margin Select Register: 0
// Pipeline Latency Select: 0
// RAM Latency Select: 0
pbist_regs[RAMT] = 0x00002000UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE400UL) = 0x4C000001UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE440UL) = 0x00000075UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE404UL) = 0x4C000002UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE444UL) = 0x00000075UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE408UL) = 0x4C000003UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE448UL) = 0x00000075UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE40CUL) = 0x4C000004UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE44CUL) = 0x00000075UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE410UL) = 0x4C000005UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE450UL) = 0x00000075UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE414UL) = 0x4C000006UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE454UL) = 0x00000075UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE418UL) = 0x00000000UL;
*reinterpret_cast<volatile Uint32*>(0xFFFFE458UL) = 0x00000001UL;
// Step 11:
// TODO: Run PBIST
pbist_regs[RSVD] = 1UL;
// Step 12:
// Wait until memory self-test done is indicated
while ((sys_regs[MSTCGSTAT] & 0x1UL) != 0x1UL);
// Get the result
Bool ret_val = false;
if(is_test_passed())
ret_val = true;
// Step 13:
// Disable PBIST clocks and ROM clock
pbist_regs[PACT] = 0x0UL;
// Step 14:
// Disable PBIST
sys_regs[MSTGCR] &= 0xFFFFFFF0UL;
sys_regs[MSTGCR] |= 0x5UL;
// Step 15:
return ret_val;