TMS570LC4357: Data received over SPI DMA (configured as slave) are swapped when EMAC is enabled

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

hi,

We have configured SPI1 as a salve and configured DMA mode to receive data. Things work fine if used only SPI in DMA mode, but when we enable Emac driver for Ethernet and do a ping or send ethernet packets, we see that data received over SPI is swapped/Out of order.

For example, If we were expecting data over SPI as 0xAAAA and 0x5555. we always get the expected data when ethernet is not enabled. But when we start using Ethernet (by integrating the EMAC driver) and do a ping, we see that data received on SPI1 is swapped/Out of order ie., we receive 0x5555 and 0xAAAA. And sometimes data swaps multiple times.

Does configuring SPI in DMA mode causing the issue when Ethernet is enabled as EMAC also uses DMA?

From the Reference manual it says, EMAC acts as a DMA master, so not sure what configuration we have to do in the EMAC or SPI to resolve this issue.

Also, we do saw errata DEVICE#54 Writes and reads to EMAC CPPI memory are byte-swapped on the big-endian device (TMS570) and ensured used 'EMACSwizzleData' function from halogen to fix this errata.

But we are not able to find what is causing the SPI data to be swapped/out of order as mentioned above.

  • Hello,

    Enabling EMAC should not impact the SPI DMA transfer. The CPU interconnect subsystem has a built-in Accelerated Coherency Port (ACP) which provides memory coherency checking between CPU and an external master. Accesses to SRAM made by the DMA PortA (SPI+DMA), and PS_SCR_M (EMAC) are first checked by the ACP coherency hardware to see if the write data is already in the CPU's data cache. 

  • Hi Wang,

    Thanks, wang for your response.

    As per your inputs, if the processor has the inbuilt capability to do a memory coherency check between CPU and external master. in that case, we agree that EMAC should not impact the SPI DMA transfer; But, we are helpless to find the root cause for this situation.

    As mentioned previously, we have configured the SPI1 with DMA in slave mode (VCLK1 90 MHZ) where the external master sends the data at 10MHz baud rate and EMAC/MDIO(VCLK3) clock is configured to 90MHz and it is used in the RMII mode. If we doubt the SPI-DMA configuration then it would have not also worked in the independent mode, but it worked appropriately when independent. As soon as we enabled the Ping/Ethernet transmission, it starts, swizzling the bits and we can see the SPIINTFLAG shows the data length error.

    In fact, we are yet uncertain what is causing this issue and how to debug/resolve it. Not able to identify whether it is an issue from SPI, DMA, or EMAC. We are actually stuck due to this issue and need your help. Quick response will be appreciated.

  • Hello Srihari,

    How easy to produce this issue? Can you share your code with us for re-producing the issue on my banch?

  • hi Wang, 

    The code is on our application, we will try to generate the halogen code and share it.

    We have further analyzed the data coming over SPI to the processor and captured the signal shown below:

    Data is sent as below (from master):

    Step1: Chip select asserted

    Step 2: 16-bits of data sent (0xAAAA)

    Step 3:  chip select d-asserted and asserted with 160 ns width

    -Step 4:16-bits of data sent (0x5555)

    Step-5: chip select de-asserted 

    Step-6: wait for 120us and the process of sending the data repeats from step1 and also the clock is configured for 10MHZ.

    From the above steps, we could make out that we are receiving 32-bits of data with chip select asserted( around 160ns) after 16-bits of transfer ( as the processor SPI is configured to receive 16-bits of data), and the delay between each 32-bit transfer is 120 us.

    As communicated earlier, processor SPI1 with DMA enabled is configured as a slave to receive 16-bit of data where HCLK, VCLK1, VCLK2, VCLK3 are running at 90 MHZ and GCLK is configured as 180MHZ. With this configuration, SPI is able to receive the data, but when we enable the EMAC driver and do a ping over ethernet we are seeing a data length error and the data received over SPI is swizzled.

    Is the processor not able to handle SPI DMA and EMAC running together? as they are working well independently.

    Regards,

    Srihari

  • Hello Srihari,

    I am trying to produce the issue using my launchpad, and it will take some time for me get the test done.

  • Hi Wang,
    when we tested the SPI1 with CS2, We were able to receive the data properly without any data length error being generated, and also it was working good when Ethernet enabled. Not able to understand why data is being received over CS2, though it is not connected, in fact it is connected to CS1 but not receiving the proper data over that chip select. Is it something that when SPI configured to slave, all chip selects receive the data though it is configured?
    Please find below the initialization we are doing with CS2, where we are receiving the data properly, let us know if anything wrong there as well
    /** bring SPI out of reset */
    spi_base[GCR0_INDEX] = 0U;
    spi_base[GCR0_INDEX] = 1U;

    /** SPI1 master mode and clock configuration */
    spi_base[GCR1_INDEX] = (spi_base[GCR1_INDEX] & 0xFFFFFFFCU) | ((Uint32)((Uint32)0U << 1U) /* CLOKMOD */
    | 0U); /* MASTER */

    /** SPI1 enable pin configuration */
    spi_base[INT0_INDEX] = (spi_base[INT0_INDEX] & 0xFEFFFFFFU)| (Uint32)((Uint32)0U << 24U); /* ENABLE HIGHZ */

    /** - Delays */
    spi_base[DELAY_INDEX] = (Uint32)((Uint32)0U << 24U) /* C2TDELAY */
    | (Uint32)((Uint32)0U << 16U) /* T2CDELAY */
    | (Uint32)((Uint32)0U << 8U) /* T2EDELAY */
    | (Uint32)((Uint32)0U << 0U); /* C2EDELAY */

    /** - Data Format 0 */
    spi_base[FMT_0_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - Data Format 1 */
    spi_base[FMT_1_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - Data Format 2 */
    spi_base[FMT_2_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - Data Format 3 */
    spi_base[FMT_3_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - set interrupt levels */
    spi_base[LVL_INDEX] = (Uint32)((Uint32)0U << 9U) /* TXINT */
    | (Uint32)((Uint32)0U << 8U) /* RXINT */
    | (Uint32)((Uint32)0U << 6U) /* OVRNINT */
    | (Uint32)((Uint32)0U << 4U) /* BITERR */
    | (Uint32)((Uint32)0U << 3U) /* DESYNC */
    | (Uint32)((Uint32)0U << 2U) /* PARERR */
    | (Uint32)((Uint32)0U << 1U) /* TIMEOUT */
    | (Uint32)((Uint32)0U << 0U); /* DLENERR */

    /** - clear any pending interrupts */
    spi_base[FLG_INDEX] |= 0xFFFFU;

    /** - enable interrupts */
    spi_base[INT0_INDEX] = (spi_base[INT0_INDEX] & 0xFFFF0000U)
    | (Uint32)((Uint32)0U << 9U) /* TXINT */
    | (Uint32)((Uint32)0U << 8U) /* RXINT */
    | (Uint32)((Uint32)0U << 6U) /* OVRNINT */
    | (Uint32)((Uint32)0U << 4U) /* BITERR */
    | (Uint32)((Uint32)0U << 3U) /* DESYNC */
    | (Uint32)((Uint32)0U << 2U) /* PARERR */
    | (Uint32)((Uint32)0U << 1U) /* TIMEOUT */
    | (Uint32)((Uint32)0U << 0U); /* DLENERR */

    /** @b initialize @b SPI1 @b Port */

    /** - SPI1 Port output values */
    spi_base[PC_3_INDEX] = (Uint32)((Uint32)1U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)1U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)1U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)1U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)1U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)1U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)0U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - SPI1 Port direction */
    spi_base[PC_1_INDEX] = (Uint32)((Uint32)1U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)1U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)0U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)1U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)1U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)1U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)1U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)1U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - SPI1 Port open drain enable */
    spi_base[PC_6_INDEX] = (Uint32)((Uint32)0U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)0U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)0U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)0U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)0U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)0U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)0U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)0U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - SPI1 Port pullup / pulldown selection */
    spi_base[PC_8_INDEX] = (Uint32)((Uint32)1U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)1U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)1U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)1U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)1U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)1U << 8U) /* ENA */
    | (Uint32)((Uint32)1U << 9U) /* CLK */
    | (Uint32)((Uint32)1U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)1U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)1U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)1U << 25U); /* SOMI[1] */

    /** - SPI1 Port pullup / pulldown enable*/
    spi_base[PC_7_INDEX] = (Uint32)((Uint32)0U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)0U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)0U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)0U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)0U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)0U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)0U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /* SPI1 set all pins to functional */
    spi_base[PC_0_INDEX] = (Uint32)((Uint32)0U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)0U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)0U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)0U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)0U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)0U << 8U) /* ENA */
    | (Uint32)((Uint32)1U << 9U) /* CLK */
    | (Uint32)((Uint32)1U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)1U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - Finally start SPI1 */

    spi_base[GCR1_INDEX] = (spi_base[GCR1_INDEX] & 0xFEFFFFFFU) | 0x01000000U;

    spi_base[DAT1_INDEX] = 0x00040000;

  • hello Shivam,

    The SPI1CS[1] (pin F3) is multiplexed with MII_COL (pin F3) on Pin F3. You can select pin W4 for MII_COL. Can you check which pin is used for MII_COL?

    SPI1CS[2] is multiplexed with MDIO on pin G3. You can select F4 as MDIO.  

  • Hi Wang,

    In our current code we have configured the pins related to this interfaces as follows:

    1) for pinmux it is,

    pinmux_pin->PINMUX[21] = PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MII_TXD_2 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_N2HET1_19;

    2) for signal we have commented the following MII related code ,as we were using the ethernet in RMII mode and we have configured the pins which are required for the RMII operation.

    //pinmux_base->PINMUX_0[89] = SIGNAL_MII_COL_F3 | SIGNAL_MII_CRS_B4;
    //pinmux_base->PINMUX_0[90] = SIGNAL_MII_RX_DV_B11 | SIGNAL_MII_RX_ER_N19 | SIGNAL_MII_RXCLK_K19 | SIGNAL_MII_RXD_0_P1;
    //pinmux_base->PINMUX[91] = SIGNAL_MII_RXD_1_A14 | SIGNAL_MII_RXD_2_G19 | SIGNAL_MII_RXD_3_H18 | SIGNAL_MII_TX_CLK_D19;

    but as you indicated, we are using F4 for mdio as :

    pinmux_pin->PINMUX[87]  = SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1       | SIGNAL_MDIO_F4;

    Please, let us know if there is update require on this as well.

  • Hi Team,

    Let us know if anyone have comments on it, waiting for your response.

    Regards,

    Shivam Kakad

  • Hi Team,

    Any update on this, actually we are stuck at this point. Need help to proceed further.

    Regards,

    Shivam Kakad

  • Hello Srihari Manthri,

    Can you please share your SPI DMA mode to receive data code? I have the same requirement, but I am unable to receive data.

    Thanks

  • I did several test with lwip demo and SPI+DMA, but I did not see this kind of issue.

  • Hi Wang,

    Can you please share us the test code and settings which you did along with the connections?

    Regards,

    Shivam

  • I did a test with EMAC loopback and MibSPI loopback with DMA. The EMAC TX and EMAC RX interrupts are enabled, but MibSPI doesn't use interrupt. So emac RX may interrupt MibSPI TX/RX transfer.


    int main(void)
    {
    /* USER CODE BEGIN (3) */
    esmREG->SR1[0] = 0xFFFFFFFF;
    esmREG->SR1[1] = 0xFFFFFFFF;
    esmREG->SR1[2] = 0xFFFFFFFF;
    esmREG->EKR = 0x0A;
    esmREG->EKR = 0x00;
    _enable_IRQ();

    _mpuInit_();
    /* - creating a data chunk in system ram to start with ... */
    loadDataPattern(D_SIZE,&TXDATA[0]);

    /* - initializing mibspi - enabling tg 0 , length 127 (halcogen file)*/
    mibspiInit();

    /* - enabling loopback ( this is to emulate data transfer without external wires */
    mibspiEnableInternalLoopback(mibspiREG1);

    /* - configuring dma control packets */
    g_dmaCTRLPKT1.SADD = (uint32)TXDATA; /* source address */
    g_dmaCTRLPKT1.DADD = (uint32)&(mibspiRAM1->tx[0].data); /* destination address */
    g_dmaCTRLPKT1.CHCTRL = 0; /* channel control */
    g_dmaCTRLPKT1.FRCNT = F_COUNT; /* frame count */
    g_dmaCTRLPKT1.ELCNT = E_COUNT; /* element count */
    g_dmaCTRLPKT1.ELDOFFSET = 4; /* element destination offset */
    g_dmaCTRLPKT1.ELSOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT1.FRDOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT1.FRSOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT1.PORTASGN = PORTA_READ_PORTB_WRITE;
    g_dmaCTRLPKT1.RDSIZE = ACCESS_16_BIT; /* read size */
    g_dmaCTRLPKT1.WRSIZE = ACCESS_16_BIT; /* write size */
    g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER ; /* transfer type */
    g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1; /* address mode read */
    g_dmaCTRLPKT1.ADDMODEWR = ADDR_OFFSET; /* address mode write */
    g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_ON; /* autoinit */

    g_dmaCTRLPKT2.SADD = (uint32)&(mibspiRAM1->rx[0].data); /* source address */
    g_dmaCTRLPKT2.DADD = (uint32)RXDATA; /* destination address */
    g_dmaCTRLPKT2.CHCTRL = 0; /* channel control */
    g_dmaCTRLPKT2.FRCNT = F_COUNT; /* frame count */
    g_dmaCTRLPKT2.ELCNT = E_COUNT; /* element count */
    g_dmaCTRLPKT2.ELDOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT2.ELSOFFSET = 4; /* element destination offset */
    g_dmaCTRLPKT2.FRDOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT2.FRSOFFSET = 0; /* frame destination offset */
    g_dmaCTRLPKT2.PORTASGN = PORTB_READ_PORTA_WRITE;
    g_dmaCTRLPKT2.RDSIZE = ACCESS_16_BIT; /* read size */
    g_dmaCTRLPKT2.WRSIZE = ACCESS_16_BIT; /* write size */
    g_dmaCTRLPKT2.TTYPE = FRAME_TRANSFER ; /* transfer type */
    g_dmaCTRLPKT2.ADDMODERD = ADDR_OFFSET; /* address mode read */
    g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1; /* address mode write */
    g_dmaCTRLPKT2.AUTOINIT = AUTOINIT_ON; /* autoinit */

    /* upto 32 control packets are supported. */

    /* - setting dma control packets */
    dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT2); //RX
    dmaSetCtrlPacket(DMA_CH1,g_dmaCTRLPKT1); //TX

    dmaReqAssign(DMA_CH0, DMA_REQ0); //RX
    dmaReqAssign(DMA_CH1, DMA_REQ1); //TX


    /* - setting the dma channel to trigger on h/w request */
    dmaSetChEnable(DMA_CH0, DMA_HW);
    dmaSetChEnable(DMA_CH1, DMA_HW);

    mibspiDmaConfig(mibspiREG1,0,0,1);

    dmaEnable();

    EMACHWInit(emacAddress);

    EMACEnableLoopback(EMAC_0_BASE);
    create_packet();
    EMACTransmit(&hdkif_data[0], &pack[0]);

    mibspiTransfer(mibspiREG1,0 );

    while(1);

    /* USER CODE END */

    return 0;
    }

    It's better for you to share your code, so we can reproduce the issue. 

  • Hi Wang,

    Our requirement is SPI1+DMA and Ethernet. As communicated in a previous post ( copied source code below for reference again), in our schematic we have CS1 of SPI1 is connected from the master. So when we receive data over SPI1 with chip select 1 configured, we always see a data length error.

    But if we configure chip select 2, and when received data over SPI1 we are not receiving any data length error. So we are still wondering why everything works well when chip select 2 is configured.

    We have also verified the hardware and tested the signals to check if Chipselect 1 has any issues, we didn't find any.

    The code provided below is configured for Chip select 2 which always works. Also, to configure chip select 1 we only update DAT1 INDEX as 'spi_base[DAT1_INDEX] = 0x00020000;' Please let me know  if we are missing any configuration below:

    /** bring SPI out of reset */
    spi_base[GCR0_INDEX] = 0U;
    spi_base[GCR0_INDEX] = 1U;

    /** SPI1 master mode and clock configuration */
    spi_base[GCR1_INDEX] = (spi_base[GCR1_INDEX] & 0xFFFFFFFCU) | ((Uint32)((Uint32)0U << 1U) /* CLOKMOD */
    | 0U); /* MASTER */

    /** SPI1 enable pin configuration */
    spi_base[INT0_INDEX] = (spi_base[INT0_INDEX] & 0xFEFFFFFFU)| (Uint32)((Uint32)0U << 24U); /* ENABLE HIGHZ */

    /** - Delays */
    spi_base[DELAY_INDEX] = (Uint32)((Uint32)0U << 24U) /* C2TDELAY */
    | (Uint32)((Uint32)0U << 16U) /* T2CDELAY */
    | (Uint32)((Uint32)0U << 8U) /* T2EDELAY */
    | (Uint32)((Uint32)0U << 0U); /* C2EDELAY */

    /** - Data Format 0 */
    spi_base[FMT_0_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - Data Format 1 */
    spi_base[FMT_1_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - Data Format 2 */
    spi_base[FMT_2_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - Data Format 3 */
    spi_base[FMT_3_INDEX] = (Uint32)((Uint32)0U << 24U) /* wdelay */
    | (Uint32)((Uint32)0U << 23U) /* parity Polarity */
    | (Uint32)((Uint32)0U << 22U) /* parity enable */
    | (Uint32)((Uint32)0U << 21U) /* wait on enable */
    | (Uint32)((Uint32)0U << 20U) /* shift direction */
    | (Uint32)((Uint32)0U << 17U) /* clock polarity */
    | (Uint32)((Uint32)0U << 16U) /* clock phase */
    | (Uint32)((Uint32)8U << 8U) /* baudrate prescale */
    | (Uint32)((Uint32)16U << 0U); /* data word length */

    /** - set interrupt levels */
    spi_base[LVL_INDEX] = (Uint32)((Uint32)0U << 9U) /* TXINT */
    | (Uint32)((Uint32)0U << 8U) /* RXINT */
    | (Uint32)((Uint32)0U << 6U) /* OVRNINT */
    | (Uint32)((Uint32)0U << 4U) /* BITERR */
    | (Uint32)((Uint32)0U << 3U) /* DESYNC */
    | (Uint32)((Uint32)0U << 2U) /* PARERR */
    | (Uint32)((Uint32)0U << 1U) /* TIMEOUT */
    | (Uint32)((Uint32)0U << 0U); /* DLENERR */

    /** - clear any pending interrupts */
    spi_base[FLG_INDEX] |= 0xFFFFU;

    /** - enable interrupts */
    spi_base[INT0_INDEX] = (spi_base[INT0_INDEX] & 0xFFFF0000U)
    | (Uint32)((Uint32)0U << 9U) /* TXINT */
    | (Uint32)((Uint32)0U << 8U) /* RXINT */
    | (Uint32)((Uint32)0U << 6U) /* OVRNINT */
    | (Uint32)((Uint32)0U << 4U) /* BITERR */
    | (Uint32)((Uint32)0U << 3U) /* DESYNC */
    | (Uint32)((Uint32)0U << 2U) /* PARERR */
    | (Uint32)((Uint32)0U << 1U) /* TIMEOUT */
    | (Uint32)((Uint32)0U << 0U); /* DLENERR */

    /** @b initialize @b SPI1 @b Port */

    /** - SPI1 Port output values */
    spi_base[PC_3_INDEX] = (Uint32)((Uint32)1U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)1U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)1U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)1U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)1U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)1U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)0U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - SPI1 Port direction */
    spi_base[PC_1_INDEX] = (Uint32)((Uint32)1U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)1U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)0U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)1U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)1U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)1U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)1U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)1U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - SPI1 Port open drain enable */
    spi_base[PC_6_INDEX] = (Uint32)((Uint32)0U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)0U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)0U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)0U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)0U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)0U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)0U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)0U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - SPI1 Port pullup / pulldown selection */
    spi_base[PC_8_INDEX] = (Uint32)((Uint32)1U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)1U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)1U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)1U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)1U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)1U << 8U) /* ENA */
    | (Uint32)((Uint32)1U << 9U) /* CLK */
    | (Uint32)((Uint32)1U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)1U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)1U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)1U << 25U); /* SOMI[1] */

    /** - SPI1 Port pullup / pulldown enable*/
    spi_base[PC_7_INDEX] = (Uint32)((Uint32)0U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)0U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)0U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)0U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)0U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)0U << 8U) /* ENA */
    | (Uint32)((Uint32)0U << 9U) /* CLK */
    | (Uint32)((Uint32)0U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)0U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /* SPI1 set all pins to functional */
    spi_base[PC_0_INDEX] = (Uint32)((Uint32)0U << 0U) /* SCS[0] */
    | (Uint32)((Uint32)0U << 1U) /* SCS[1] */
    | (Uint32)((Uint32)1U << 2U) /* SCS[2] */
    | (Uint32)((Uint32)0U << 3U) /* SCS[3] */
    | (Uint32)((Uint32)0U << 4U) /* SCS[4] */
    | (Uint32)((Uint32)0U << 5U) /* SCS[5] */
    | (Uint32)((Uint32)0U << 8U) /* ENA */
    | (Uint32)((Uint32)1U << 9U) /* CLK */
    | (Uint32)((Uint32)1U << 10U) /* SIMO[0] */
    | (Uint32)((Uint32)1U << 11U) /* SOMI[0] */
    | (Uint32)((Uint32)0U << 17U) /* SIMO[1] */
    | (Uint32)((Uint32)0U << 25U); /* SOMI[1] */

    /** - Finally start SPI1 */

    spi_base[GCR1_INDEX] = (spi_base[GCR1_INDEX] & 0xFEFFFFFFU) | 0x01000000U;

    spi_base[DAT1_INDEX] = 0x00040000;