TMS570LC4357, detect single bit error in L2FMC and L2RAM

Hello Lars,

The ECC is enabled by default, any single-bit ECC error is corrected during reading. For error in SRAM, the corrected data is written back to SRAM too. The single-bit error doesn't go to ESM except for the following two cases:

1. Single-bit error during implicit reading (read TI OTP) (ESM 1.6)

2. Single-bit ECC error during CPU writing SRAM (ESM 1.26)

Hi,
 
I know that ECC is enabled by default and that single bit errors are corrected.
But I want to detected single bit errors in L2FMC and L2RAM.

I found the following sentence in the reference manual (spnu563.pdf):
“If the SERRENA bits in EPCCNTRL register are enabled, the singlebit error correctable fault event will be triggered to ESM.”
For me it seems that I have to activate the SERRENA Bit, I can do that in my software by calling the function “epcEnableSERREvent”.
But is that enough to detect single Bit erros in L2FMC ? And if I do it in this way what kind of ESM interrupt channel is trigger ?

The same for L2RAM, I found the register “RAMCTRL”, Bit 4 “CPUWSC”. I think if I set bit CPUWSC  to “1” (Enable single bit error status capture and ESM notification.) single
bit error on L2RAM are detected and if an single bit error is detected ESM 26 is activated.

I don’t know if I am on the right way.

Best regards
Lars