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RM48L952: Controlling EMIF in asynchronous mode

Other Parts Discussed in Thread: HALCOGEN

o here's the situation: I have a system where RM48 and cpld are connected via EMIF like picture below.

Please note that EMIF_WAIT, EMIF_nDQM, EMIF_BA pins are not connected. This system is built a while ago and I'm trying to reuse the board.
I understand that since EMIF_BA pins are not connected, I will have to increment 4 bytes in program address to actually access address 1 incremented.

After configuring EMIF(and enabled driver in driver enable section) in halcogen and intializing in program, I wrote code to write value to address 0x00:

*((uint8_t*)0x60000000) = (uint8_t)0xff;

My instincts tell me that EMIF should set address 0, data 0xff and write enable 1 time to write the byte to address. Instead the program send out 5 write enables with incrementing address and writes undefined values to those memories:

Because it writes undefined values after real value to same 32 bit aligned address, it overwrites intended value and write unknown value to next address. Sometimes it sends out 5 bytes, sometimes 2 bytes. When I write 32 bit data, sometimes it writes 4 and in other occasions 5 bytes. It doesn't seem to be consistent.

After re-reading the reference manual, I found that EMIF_nDQM does "byte enables". While I couldn't find what does that exactly mean, I suspect that byte enable will only be become active when emif is sending correct address that I intended to write. If that is the case then connecting EMIF_nDQM will solve the problem, but I have boards which are already manufactured this way and making new ones again will be a difficult decision to make. I wonder if there is any workaround to control EMIF more precisely without changing the design, such as controlling number of WE sending out.

In summary,

1. Does "byte enables" enable which WE signal is valid?

2. Is there any way to control WE signal or any other way to write and read value safely in my situation?