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MSP430FR5969-SP: FRAM ECC Information

Part Number: MSP430FR5969-SP

I am trying to find details about the operation of the MSP430 FRAM's ECC. Specifically, the memory block size that is protected against single bit errors. (i.e. Can it correct a single bit error inside of every byte? Word? etc.)

  • Since the FRAM cache is 64 bits wide, that would be what I would bet on.

  • Thanks, David. That seems logical.

    Maybe a TI rep can confirm this with documentation.

  • Hey Aaron,

    I was under the impression that it was every 16-bit address, but I couldn't confirm this in any of the FRAM documentation.  Let me check with our systems team and try and get this confirmed if it's 16-bit or slightly larger.  

    Thanks,

    JD

  • Hi JD,

    Thank you for looking into this. 

    Best regards,

    Aaron

  • Hey Aaron,

    I was under the impression that it was every 16-bit address, but I couldn't confirm this in any of the FRAM documentation.  Let me check with our systems team and try and get this confirmed if it's 16-bit or slightly larger.  

    Thanks,

    JD

    Hi JD,

    Have you been able to find some documentation on this?

    Thanks, Aaron

  • Hey Aaron,

    I was able to get some feedback from our system team.  The FRAM word size is actually 80 bits (64 bits of data, 16 bits of ECC).  The 16-bit ECC gives you dual error correct and triple error detect (DECTED), which is better than the normal 8 ECC bits per 64 data bits which gives you SECDED.  For FRAM, all dual-bit errors within a 64-bit data word (64-bit aligned) are corrected on the fly (because it is FRAM) and they set the DED flag in the device.  Triple bit errors within a 64-bit word are not correctable and would result in real corruption.

    Hope this addresses all the customers questions!

    Thanks,

    JD

  • Hey JD,

    That is great news. Even better than expected. So, you're saying that the ECC on the MSP430FR5969-SP is upgraded compared to the rest of the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family, which can only correct single bit errors (SECDED). 

    It would be really great to have documentation for this. Are you confident enough in this answer (DECTED w/ 80 bit frame) that we can design based on it ("Take it to the bank", so to speak)?

    Is there any way for us to introduce errors into the FRAM and bypass the ECC so that we can test it?

    Best regards, Aaron

  • Hello,

    There is nothing upgraded on the FRAM of MSP430FR5969-SP compared to the commercial versions of the devices.  This ECC functionality will apply to all FR59xx, FR6xx, and FR2xx devices.  My understanding is that this enhanced ECC was added to these FRAM families mainly for additional protection from FRAM Thermal Depolarization during soldering reflow.  

    I'm confident in this information but as for documentation, unfortunately, we don't currently provide many details on the ECC implementation.  I will raise this with the Systems engineering team and see if this is something that they can look at adding to these FRAM devices.

    As for testing, I don't know of any way to forcibly introduce errors into the FRAM to evaluate the ECC.   

    Thanks,

    JD

  • JD,

    I think my question about the upgrade was based on a misconception I had. For some reason I thought that the family specifically indicated that it had SECDEC which would have contradicted the DECTED. Now I see that the statements are generalized, so everything is in agreement. 

    Thank you very much for your help in clarifying this issue.

    Best regards, Aaron