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MSP430FR2433: Interrupt Processing

Part Number: MSP430FR2433

When three high to low or low to high signals rapidly set the same maskable IFG before its ISR can be executed, will those three interruptions, of the same priority, be placed into a queue by the interrupt system, or will there be just one pending interruption for all three flags.

For example, the P1.0 channel is rapidly signaled to set three times before its ISR can be executed, While the first P1.0 interruption is pending, will the next two P1.0 interruptions be put in a queue and become pending?

This question is in the context of using a delay instruction in the ISR to handle a bouncing switch.