MSP430F6726A: Laminated chip varistor for anti-static measures

1. Why you consider to add the varistor? Because there will be cables connected to these pins?

 2. The only consideration is that the varistor will affect the signal setup time. I will advise the value should close to the pull-down capacitor on reset pin.

Hi, Eason Zhou

We apologize for the inconvenience, but the JTAG terminal signal was not damaged. Forget the above question.
However, after the electrostatic test, the voltage of the 26-pin LCD CAP terminal dropped from 3.6V to 1.86V, which is half of the voltage. It does not recover even if you reset it.
As a result, the LCD became extremely dark.
Can you guess which terminal was broken?

Thanks,

Koki

I think there may be something wrong with the voltage generate part. 

Can you check the voltage input for your bias mode. You can use  LCDREXT to output every level voltage to the external pin.

Hi, Eason

I think the cause is overvoltage to VDCC. Therefore, I am thinking of putting a varistor in DVCC as an EOS countermeasure.

1) Is there anything I should be careful about when inserting the varistor?

2)Also, please let me know if there are other countermeasures.

Thanks,

I advice you add a 3.3V TVS diode