Hi experts,
The following questions about TimerA and DMA could not be confirmed from the document, so I would appreciate it if you could tell me about them.
[TimerA]
The time chart for the capture mode with SCS=1 is shown in "Figure 25-10. Capture Signal (SCS = 1)" in User's Guide (Rev. P).
Q1: If SCS = 1, is it correct that the capture is triggered by the falling edge of the timer clock?
Q2: Assuming that the capture is triggered on falling edge, is the following idea correct?
If CCI fluctuates at the timing of timer clock = HIgh, the count value at that point will be captured.
If the CCI changes at the timing of timer clock = Low, the count value at the state advanced by one clock cycle is captured.
Q3: If SCS = 0, is it correct that the capture is triggered at the same time as the timing of CCI change?
[DMA]
Currently, the FRLPMPWR bit is set to 0 in order to respond to the errata PMM29. In this case, it is stated that a wait time of "twake-up workaround = twake-up LPM3 + twake-up FRAM" is required at startup.
Q4: Does this concept of wait time also need to be taken into account when DMA transfer is triggered by a timer during LPM (no interrupt processing is used)?
Note that the source of the DMA transfer is a variable on the SRAM and the destination is the POUT register of the IO port.
Best regards,
O.H