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MSP430FR2433: Phase ambiguity between 2 timers

Gerald Harron
Prodigy 40 points
Part Number: MSP430FR2433

Observation: When using Timer0_A3 and Timer1_A3 both driven from SMCLK it is observed that the phase relationship of the 2 output is not always constant, such as caused by a power interruption.

Purposed Solution: Use Timer0_A3 output as an input to Timer1_A3.

Problem is understanding how to do this.  The Family guide 13.2.1.1 indicates " The timer clock can be sourced from ACLK, SMCLK, or externally from TAxCLK or INCLK." , as I believe it is shown in Figure 1-6 for example.  I am unclear of the code to provide the internal or external connection.

For example I have working code for Timer0_A3 to drive P1.1 as follows

    //setup hardware clock output to P1.1
    TA0CCR0 = (16*8)-1;                                                // PWM Period
    TA0CCTL1 = OUTMOD_7;                                        // CCR1 reset/set
    TA0CCR1 = 16*4;                                                      // CCR1 PWM duty cycle
    TA0CTL = TASSEL__SMCLK | MC__UP | TACLR;  // SMCLK, up mode, clear TAR

Then the 2nd part is to connect the Timer0_A3 output to Timer1_A3 input and produce an interrupt based on Timer1_A3 (which does not work). I believe I am missing out on understanding the code to make the internal or external connection of the timers.  If I am limited to external connection, can I control which pin? or it is perhaps limited to P1.6 as shown in Table 6-12 of the MSP430FR3422 datasheet

    //setup interrupt to control the On/Off Timing
    TA1CCTL0 = CCIE;                                                                            // TACCR0 interrupt enabled
    TA1CCR0 = (16*200)-1;                                                                    //Period
    TA1CTL = TASSEL__TACLK  | ID__8 | MC__CONTINUOUS;        // setup external input, /8
    //TA1CTL = TASSEL__INCLK | ID__8 | MC__CONTINUOUS;        // setup internal input, /8

  • 0
    Guru 88700 points

    In your problem statement ("Observation") are you saying that for two separate (identically-configured) timers: (a) the outputs are out of phase with one another or (b) the phase relationship between the two outputs varies over time? (a) is more or less expected behavior, since it's not easy to start two timers at the same moment (modulo cycle period). I don't think ever I've observed (b).

    In the Solution, it appears you're cascading two timers, i.e. one serves as what amounts to a pre-scaler for the second. The MSP430 doesn't provide an internal channel to do this, you'll need to run a patch wire from TA0.1 (P1.1) to TA1CLK (P1.6). When I've done this it acted as expected.

  • 0 in reply to Bruce McKenney47378
    Prodigy 40 points

    The timers are not identically configured.  The 1st one for example could be 4us, while the 2nd might be 200us. The original clock is 16MHz. Since both are dividing down from the 16MHz if one clock cycle gets lost in one divider the relationship between the two clocks changes.  The relationship is normally constant, unless disturbed.

    I had tried doing an external connection from P1.1 to P1.6 but that did not seem to be enough as I did not get an interrupt. I think I am missing something simple in the code in configuring P1.6 to TA1CLK, or is this automatic?

  • 0 in reply to Gerald Harron
    Prodigy 40 points

    Ah, problem found. I was missing:

    P1SEL1  |= BIT6;

  • +1 in reply to Gerald Harron
    Guru 88700 points

    To configure P1.1 as TA0.1, you need PSEL=10 and DIR=1. For TA1CLK it's PSEL=10 and DIR=0. [Ref data sheet (SLASE59D) Table 6-17.

    My arithmetic says to expect the first TA1CCR0 interrupt at (16*8*8*16*200) SMCLK ticks (about 3.2 sec with SMCLK=1MHz). The next would follow it after (16*8*8*65536) SMCLK ticks (about 67 sec at SMCLK=1MHz).

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