MSP430FR2111: BSL Question

Lee hyunjun

Part Number: MSP430FR2111

I use hw sequency to enter bsl.
Then send below data for mass erase
"0x80 0x21 0x00 0x11 0xFF ... 0xFF 0x9E 0xE6"
When transmission is not completed ("0x80 0x21 0x00 0x11" timing), "0x51 0x51 0x51" data is received from bsl.

What are these causes?
How can I solve this?

over 2 years ago

0 Lee hyunjun over 2 years ago

Prodigy 50 points

Do I need a SYNC or handshake after entering BSL?
please tell me how if needed

0 Lee hyunjun over 2 years ago

Prodigy 50 points

If tx packet is sent after 50ms delay, rx packet is received as shown below.
Is this the correct way?
If so, what is the appropriate delay?
Why are ACK and rx data 40ms apart?

0 James Evans over 2 years ago in reply to Lee hyunjun

TI__Mastermind 49692 points

Hi Lee,

According to page 18 in the MSP430 FRAM Devices Bootloader (BSL) User's Guide, the BSL on the FR4xx, FR21xx, and FR20xx MCUs does not support the Mass Erase command.

0 Lee hyunjun over 2 years ago in reply to James Evans

Prodigy 50 points

I know. This has already been confirmed.
So I am trying to erase with RX Password(0x11) instead of mass erase(0x15).
The gist of the question is why the delay after entering the BSL is necessary.
There is no mention of this delay anywhere in the documentation.

It takes almost a day to get an answer because of the time difference.
Please read my question carefully.

0 James Evans over 2 years ago in reply to Lee hyunjun

TI__Mastermind 49692 points

We do not have a specification for minimum time between BSL invocation and starting communication. The CPU speed runs at 8-MHz, and there will be time required to start the BSL. For some devices, the FLL lock will also take some time.

MSP430FR2633: Confirm the start timing of communication after BSL sequence

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MSP430FR2111: BSL Question