Other Parts Discussed in Thread: MSP430F67641
Dear Team,
I am interfacing an RF module through Asynchronous UART at 9600 baudrate. My RF module is receiving data every 2 seconds once and writing out to be read by the controller MSP430F67641.
The problem i face is that, whenever i place a breakpoint in my code, i get an overrun error set (UCOE and UCRXERR set) and i am no longer able to receive any data anymore until i hit a full reset.
I do not get this issue while i do not halt the target with breakpoints and allow it to run continuously. I know that if i halt the core with a breakpoint, the external RF still receives some data and writes the data to the controller and there is surely some data missed to be received. But i expected that UART module is also be paused without receiving anything and just the intermediate data is lost instead of a overrun error.
I did not notice this strange overrun behaviour in the other MSP430 controllers i used in other projects while in breakpoint.
Attached the key parts of my code. Could you please help here ?
Thanks
Surya
void SetClock_24Mhz() { SetVCore(3); // Setup UCS UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO UCSCTL5 |= DIVS__2 | DIVA__4 | DIVM__1; UCSCTL4 |= SELM__REFOCLK | SELS__REFOCLK | SELA__REFOCLK; /* 24MHz MCLK, 12MHz SMCLK, ACLK (6Mhz)*/ __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; // Select DCO range 24MHz operation UCSCTL2 = FLLD_1 | 732; // Set DCO Multiplier for 24MHz // (N + 1) * FLLRef = Fdco // (732 + 1) * 32768 = 24MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop __delay_cycles(250000); __delay_cycles(250000); __delay_cycles(250000); __delay_cycles(250000); // Loop until XT1, XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags } while (SFRIFG1 & OFIFG); // Test oscillator fault flag SFR_clearInterrupt(SFR_OSCILLATOR_FAULT_INTERRUPT); SFR_enableInterrupt(SFR_OSCILLATOR_FAULT_INTERRUPT); __delay_cycles(250000); } void Uart_Init_9600() { // Setup P2.2 UCA2RXD, P2.3 UCA2TXD P2SEL |= BIT2 | BIT3; // Set P2.2, P2.3 to non-IO P2DIR |= BIT2 | BIT3; // Enable UCA2RXD, UCA2TXD // Setup eUSCI_A2 UCA2CTLW0 |= UCSWRST; // **Put state machine in reset** UCA2CTLW0 |= UCSSEL__SMCLK | UCRXEIE; // SMCLK (12Mhz) accurate -> 12009472 Hz /* * Baud Rate calculation (9600) [PAge No- 586 user guide 2433] * 12009472/(9600) = 1250 [Greater than 16. So proceed with next calc's] * (1250.987/16) = 78.186 => (UCA1BR0 = 78) * * UCBRFx = (0.186*16) = 2.98 => 3 roundoff * User's Guide Table 22-4: Decimal value of (0.00) is UCBRSx = 0x00 */ UCA2BRW = 78; // 24MHz 9600 UCA2MCTLW = UCBRF_3 | UCOS16; // Modln UCBRSx=0, UCBRFx=0x13, UCA2CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** UCA2IE |= UCRXIE; // Enable USCI_A2 RX interrupt } #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) #pragma vector=USCI_A2_VECTOR __interrupt void USCI_A2_ISR(void) #elif defined(__GNUC__) void __attribute__ ((interrupt(USCI_A2_VECTOR))) USCI_A2_ISR (void) #else #error Compiler not supported! #endif { switch (__even_in_range(UCA2IV, USCI_UART_UCTXCPTIFG)) { case USCI_NONE: break; // No interrupt case USCI_UART_UCRXIFG: // RXIFG UCA2_Status = UCA2STATW; if (UCA2_Status & UCRXERR) { // This part of code is hit when i set a breakpoint and some data is receiveid during that time DummyRX = UCA2RXBUF; // Dummy read to clear out data UARTErrorCnt++; } else { UartRxBuff[UartRxCnt] = UCA2RXBUF; // TX -> RXed character /* Check if new line received and set processing flag */ if(UartRxBuff[UartRxCnt] == 0x0A) { UartRxFlg = true; } UartRxCnt++; } /* If RX buffer exceeds then process and flush garbage data */ if(UartRxCnt >= UartRxBuffMAX) { UartRxCnt = UartRxBuffMAX; UartRxFlg = true; } break; case USCI_UART_UCTXIFG: break; // TXIFG case USCI_UART_UCSTTIFG: break; // TTIFG case USCI_UART_UCTXCPTIFG: break; // TXCPTIFG default: break; } }