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MSP430F2013: ACLK DIV not working when LPM3???

Steve Wenner
Genius 3190 points
Part Number: MSP430F2013

Hello all...

Using an EZ430-2013 dev board with the following small app code .....

I am finding that if I port out the ACLK (the code below has this line removed P1SEL |= BIT0; as I was just using the LED on the dev board) and remove LPM3_bits below the divisor works just fine but when I put LPM3_bits back into the code the ACLK (which is assigned the VLO clk) never changes its' frequency....Can someone tell me why?

int main(void)
{
    BCSCTL1 |= DIVA_3;                        // ACLK/2
    BCSCTL3 |= LFXT1S_2;                      // ACLK = VLO
    WDTCTL = WDT_ADLY_1000;                   // Interval timer
    IE1 |= WDTIE;                             // Enable WDT interrupt

    P1DIR |= 0x01;                            // Set P1.0 to output direction

    __bis_SR_register(LPM3_bits + GIE);       // Enter LPM3 w/interrupt
}

#pragma vector=WDT_VECTOR
__interrupt void watchdog_timer(void)
{
    P1OUT ^= 0x01;                            // Toggle P1.0 using exclusive-OR
}

  • 0
    TI__Genius 9970 points

    Hi Steve,

    Please help me understand what you mean by:

    Steve Wenner said:
    ACLK (which is assigned the VLO clk) never changes its' frequency

    Also, if I understand correctly you are trying to run the watchdog from ACLK. However, you must set WDTCTL.WDTSSEL = 1 to make this happen. This may explain why entering LPM3 is affecting the behavior: LPM3 disables SMCLK which is currently clocking the watchdog.

    Regards,

    Evan

  • 0 in reply to Evan Lew
    Genius 3190 points

    Hi Evan...

    Referring to the code above....BCSCTL3 assignment sets the ACLK output to VLO (see userguide for this).  the WDTSSEL gets set via macro WDT_ADLY_1000 (supplied by TI in their msp430 files.  i am not using SMCLK here using ACLK.  Basically I ported ACLK out and it is working as expected when I get rid of LPM3 (meaning divisor BCSCTL1 setting works)....Add LPM3 into the mix and it no longer works)

    Thanks

  • 0 in reply to Steve Wenner
    TI__Genius 9970 points

    Steve,

    Thanks for the info. I think that the macro you are using is probably setting WDTCTL.WDTSSEL = 0 based on what I've seen in the msp header files I've looked through. Please confirm in your environment.

    #define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0)

    Even though you aren't using SMCLK for anything else I think the watchdog is defaulting to SMCLK as the clock source (see image below). As I noted above, SMCLK isn't available in LPM3. 

    Please try setting WDTCTL.WDTSSEL = 1 and see if it changes the behavior.

    Regards,

    Evan

  • 0 in reply to Evan Lew
    Genius 3190 points

    Evan....

    The macro I am calling is:

    /* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_1000       (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL)                 /* 1000ms  " */

    Where it calls WDTSSEL:

    #define WDTSSEL                (0x0004)

    BUT I did uncover something while doing that little experiment.....When I download and hit run from the debugger it works as if the divisor does not exist HOWEVER if I pause the debugger then run again it seems to work fine....

    Clearly the registers are ok but something with the debugger ....

    Thanks for the help

    Steve

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