MSP430F4152: MSP430F SERIES OF MICROCONTROLLERS

Teraoperations per second? Hah! You kid, right?

Can you please clarify your questions? I'm not familiar with your terminology. If you have a specific question about the data rate of a protocol I can assist you with that.

Regards,

Evan

Recent US regulations (3A090) on Integrated Circuits exported to China must meet the following parameters: aggregate bidirectional transfer rate over all inputs and outputs must be less than 600Gbyte/s with Tera Operations per seconds (TOPS) of less than 8. 

Following is the regulation: 

Commerce Control Regulation

3A090 Integrated circuits as follows (see List of Items Controlled). License Requirements Reason for Control: RS, AT Control(s) Country Chart See Supp. No. 1 to part 738) RS applies to entire entry China (See § 742.6(a)(6)) AT applies to entire entry AT Column 1 List Based License Exceptions (See Part 740 for a description of all license exceptions) LVS: N/A GBS: N/A List of Items Controlled Related Controls: See ECCNs 3D001 and 3E001 for associated technology and software controls. Related Definitions: N/A Items:

1. Integrated circuits that have or are programmable to have an aggregate bidirectional transfer rate over all inputs and outputs of 600 Gbyte/s or more to or from integrated circuits other than volatile memories, and any of the following: a.1. One or more digital processor units executing machine instructions having a bit length per operation multiplied by processing performance measured in TOPS, aggregated over all processor units, of 4800 or more; a.2. One or more digital ‘primitive computational units,’ excluding those units contributing to the execution of machine instructions relevant to the calculation of TOPS for 3A090.a.1, having a bit length per operation multiplied by processing performance measured in TOPS, aggregated over all computational units, of 4800 or more; a.3. One or more analog, multi-value, or multilevel ‘primitive computational units’ having a processing performance measured in TOPS multiplied by 8, aggregated over all computational units, of 4800 or more; or a.4. Any combination of digital processor units and ‘primitive computational units’ whose calculations according to 3A090.a.1, 3A090.a.2, and 3A090.a.3 sum to 4800 or more. Note: Integrated circuits specified by 3A090.a include graphical processing units (GPUs), tensor processing units (TPUs), neural processors, in-memory processors, vision processors, text processors, coprocessors/accelerators, adaptive processors, field-programmable logic devices (FPLDs), and application-specific integrated circuits (ASICs). Examples of integrated circuits are in the Note to 3A001.a. Technical Notes: 1. A ‘primitive computational unit’ is defined as containing zero or more modifiable weights, receiving one or more inputs, and producing one or more outputs. A computational unit is said to perform 2N-1 operations whenever an output is updated based on N inputs, where each modifiable weight contained in the processing element counts as an input. Each input, weight, and output might be an analog signal level or a scalar digital value represented using one or more bits. Such units include: - Artificial neurons - Multiply accumulate (MAC) units - Floating-point units (FPUs) - Analog multiplier units - Processing units using memristors, spintronics, or magnonics - Processing units using photonics or nonlinear optics - Processing units using analog or multilevel nonvolatile weights - Processing units using multi-level memory or analog memory - Multi-value units - Spiking units 2. Operations relevant to the calculation of TOPS for 3A090.a include both scalar operations and the scalar constituents of composite operations such as vector operations, matrix operations, and tensor operations. Scalar operations include integer operations, floating-point operations (often measured by FLOPS), fixed-point operations, bit-manipulation operations, and/or bitwise operations. 3. TOPS is Tera Operations Per Second or 1012 Operations per Second. 4. The rate of TOPS is to be calculated at its maximum value theoretically possible when all processing elements are operating simultaneously. The rate of TOPS and aggregate bidirectional transfer rate is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the threshold of 4800 bits x TOPS can be met with 600 tera integer operations at 8 bits or 300 tera FLOPS at 16 bits. The bit length of an operation is equal to the highest bit length of any input or output of that operation. Additionally, if an item specified by this entry is designed for operations that achieve different bits x TOPS value, the highest bits x TOPS value should be used for the purposes of 3A090.a. 5. For integrated circuits specified by 3A090.a that provide processing of both sparse and dense matrices, the TOPS values are the values for processing of dense matrices (e.g., without sparsity). b. [Reserved] 3A101 Electronic equipment, devices, “parts” and “components,” other than those controlled by 3A001, as follows (see List of Items Controlled). License Requirements Reason for Control: MT, AT Control(s) Country Chart (See Supp. No. 1 to part 738) MT applies to entire entry MT Column 1 AT applies to entire entry AT Column 1 List Based License Exceptions (See Part 740 for a description of all license exceptions) LVS: N/A GBS: N/A List of Items Controlled Related Controls: See also ECCN 3A002.h for controls on analog-to-digital “electronic assemblies,” modules or equipment.

Thank you Evan.  This resolves my question.

Regards,

Carmen