MSP430F4618 crystal matching

Hello,

i am currently on kind of the same issue.

I am using the RTC with an 32.. kHz clock oscillator attached to the XT1 pins of my msp430f5437A.

I have no external capacitors on my board, so i can only use the internal ones from TI, which i can set via a Control Register ( ~ 4 ... 12 pF)

Now what happens if I dont hit the exact load capacitor wished by the oscillator-datasheet is, that the clock runs slightly faster than 1 second or slightly slower than 1 second, so it has nothing to do with accuracy but with trimming. Until now i couldnt find out for myself how to hit exactly 1 second timings, but i think i will find that solution next week, so watch out for further postings if you are interested.

Hope that could give some hints to You.

Greetings, Seb

Hi Seb,

Despite the setting to internal 10pF, the result from the matching test from crystal manufacturer shows that lower load cap yield better ppm than the higher load cap.

seb said:

if I dont hit the exact load capacitor wished by the oscillator-datasheet is, that the clock runs slightly faster than 1 second or slightly slower than 1 second, so it has nothing to do with accuracy but with trimming.

Jens-Michael Gross said:

if I dont hit the exact load capacitor wished by the oscillator-datasheet is, that the clock runs slightly faster than 1 second or slightly slower than 1 second, so it has nothing to do with accuracy but with trimming.

That's why I use an external trimming capacitor to pull the crystal where I want it. This way I'm better than 0.2s/day which is <2.3ppm

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Hi Jens,

Any idea on the reason that the internal load capacitance could be so much of difference from the datasheet specified? Without the external capacitor, the ppm can goes as high as 90ppm for 12.5pF crystal when CAPX= 3h. However, deviation improves to ~40ppm when 7pF crystal is used at CAPX=3h. Assumption of PCB traces of 2pF added should gives a 11pF when CAPX=3h, thus 12.5pF crystal should match better than 7pF?

It is not (only) a matter of 'being close'.

Basically, the crystal is a mechanical capacitor. So when oscillating, charge flows from one load capacitor through the crystal to the other capacitor and back. So the three need to match for optimum charge flow. It's a charge pendulum. If you 'block' the pendulum, you slightly adjust the frequency. But you also dampen the amplitude (in case of the crystal in both directions, as charge that cannot flow through the crystal adds a DC offset to the signal) which affects the signal detection 8and the detection moment when the detector is triggered) and therefore the tiem the injector (on the othe rside of the crystal) injects additonal charge to compensate for resistive losses. The relations is far more complex than just a proximity of values. And stuff for a whole shelf of books (litteraly)

The rate of the charge and discharge would be determined by the capacitor and the kick start time lies with the ESR. Thus there is need to match the capacitance value in order to get the right sync. In theory, matching the same capacitance should match alright. Non match might be due to the parasitic effect lies with the PCB traces, temperature etc which in fact, the capacitance value is higher. However in this case, the ppm does not improves with increase of crystal load capacitance.
SLAA225 indicates that the deviation improves with increase of load capacitance. The experiment was done with no external capacitor used. Deviation is in terms of 44.2ppm for 6pF crystal, and 42.4ppm for 12.5pF. Of course this is assuming perfect crystal. If the crystal are really performing ideally, does this indicates that the internal cap value of the device is not accurate and the deviation of ~40ppm is within specification? 
Correct me if the concept is wrong on crystal capacitance matching.

123 said:

The rate of the charge and discharge would be determined by the capacitor and the kick start time lies with the ESR.

The rate of charge and dischare is primarily determined by the crystals mechanical constant. The capacitors are to allow an oscillation without having to pump in energy at large. However, if they do not precisely match the internal capacitance of the crystal, you'll have an offset voltage or an attenuation on the resulting voltage over teh capacitors, which affects the moment the inverter triggers and therefore the timing of the part that compensates the losses by ESR and the detection itself. So how a detuned capacitor affects precision depends on the oscillator circuit.

Imagine yourself sitting in a bathtub. If you sit exactly in teh middle and move a bit fore and back, you'll create an oscillation. You'll notice that you will almost instantly find a mmovement frequency in which your full force comes back to you and you don't have to add much energy to be shaken more than you wanted. And you'll see waves at both ends that may easily overboard. If you try to change the frequency, you'll see that it isn't easy at all. Your own force works against you. Now move from the middle of the bathtub towards one end. You'll instantly see that the force that keeps you at this frequency vanishes. Also, the waves at the ends shrink down significantly. this happens if the 'capacitors' don't match. Also, if the bathtub is stretched, you'll see that the waves at the end are smaller than before (this is the effect of ESR).
Also, if you cover the water with a plank on one side. Suddenly you are 'detuned', the oscillation won't start. This is a too small capacitor. And if you have a bathtub that is much deeper on one end than on the other, you'll see that the waves will be shallow on this end. This is the effect of a too large capacitor. The detector won't be able to detect the oscillation in time or fails to detect it at all.

123 said:

SLAA225 indicates that the deviation improves with increase of load capacitance.

Well, you can read through shelves of books about crstals. Only a few people who work with them did really understand what they're doing. Even I have only scratched the surface.

123 said:

does this indicates that the internal cap value of the device is not accurate

And you're right, PCB traces, crosstalk, even the GND layer on the other PCB side may increase the parasitic capacitance - and will likely be unbalanced if you don't force it to be balanced by a shielded symmetrical design around the crystal and its traces.