This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Generating Clock Pulses using MSP430F2350

Other Parts Discussed in Thread: MSP430F2350

Hello Friends

Am working on a project where i have to generate chain of pulses as printed below. I have to generate SOF and EOF

For starting a frame, i want to generate clock pulses as below with the following duration

Am using below document  as reference.

I couldnt able to generate the above pulses with the present MSP430F2350 am using.

Help appreciated



  • You can do this by using two timers and an external 'gate'. One timer generates the 423,75kHz frequency, while the other  produces the timing for the on/off. If you manage to clock the whole system with 423,75kHz*8, you can directly set SMCLK to fsystem/8 and directly output it to a port pin without needing a timer. This means, your system will run on 3.39MHz at max. If this is not okay, you'll need to set up a tiemr for generating the frequency by using the CCR0 unit in compare mode.

    The on/off timing is preformed by programming a timer for the necessary delays in compare mode. After a given number od tiemr ticks, the tiemr output signal will toggle and an interrupt is triggered. In the interrupt you can set the timer for th enext toggle. The output signal is used to control an external gate circuit (e.g. a transistor, or a TTL latch), so that the HF signal passes the latch or not.

    This is the only way to perform the above puls esequence with 100% exact timing. Every other approach will introduce jitter or latency times.

  • Hi Nanda,

    I couldn't tell for sure from your message, but are you willing to choose another MSP430?

    If so, an MSP430 with DMA would do this job nicely. You could set up an array of toggle times (~65 toggles in the SOF sequence) in advance (even store in flash if you like) and just have the DMA controller move each value into the CCR when triggered by the CCIFG.  No external latch / gate required.

    As long as MCLK is enough faster (say 10x for a safety margin) than 423,75kHz x 2, you'd be all set.  You need a 13,65MHz source somewhere anyway, so that would be perfect.  MCLK wouldn't have to be that fast at other times.  Lots of the '2xx MSP430's that have DMA also have an XT2 where you could feed the 13,65MHz crystal.