MSP-EXP430F5529LP: Problem with achieving/maintaining coherent USCI B0 SPI communications using an external crystal at XT2 (w/ 16MHz Freq).

Hi Ronnie Wright

I can understand there is some issue on SPI communication using USCI B0 on MSP-EXP430F5529LP launchpad.

May I konw this SPI is master or slave? and what is the baud rate of SPI?

as the reference, you can check the SPI example code on MSP430F552x C Examples (IAR and CCSv4) (zip)  — 240 K

Thanks!

Hello Xiaodong Li

 Thanks for your response, and thanks for your code examples. We will review them, and determine how they can be applied.

Regarding your questions below:

The SPI rate that we are trying to achieve is 16MHz.

The SPI bus is being driven from the Master (MSP430F5529).

Clock Setup Details:

ACLK sourced from XT1 (32kHz)

SMCLK sourced from XT2 (16MHz Crystal w/ built-in 15pF caps)

MCLK sourced from XT2( 16MHz …..)

Observations:

These 4-MHz initializations work:

UCS_initClockSignal(UCS_MCLK,  UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_4);

UCS_initClockSignal(UCS_SMCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_4);

SPI bus is sourced from undivided SMCLK (i.e. SPI bus rate is 4MHz)

These 8-MHz initializations work:

UCS_initClockSignal(UCS_MCLK,  UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_2);

UCS_initClockSignal(UCS_SMCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_2);

SPI bus is sourced from undivided SMCLK (i.e. SPI bus rate is 8MHz)

These 16-MHz initializations DO NOT work:

UCS_initClockSignal(UCS_MCLK,  UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_1);

UCS_initClockSignal(UCS_SMCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_1);

SPI bus is sourced from undivided SMCLK (i.e. SPI bus rate is 16MHz)

Using a SPI analyzer, we notice the following:

(1) Master SPI device data is correctly transmitted to Slave SPI device.

(2) Slave SPI device writes correct data to SPI Bus.

(3) The MSP430F5529 (Master SPI device) does not read (interpret) the SPI data correctly.

(4) The MSP430F5529 (Master SPI device) reads in a shifted version (1 bit to the right) of the correct SPI bus data.   

As an Example:

SPI Bus has: HEX (54 43 41 4E)

F5529 reads: HEX (27 20 21 2A)

SPI Bus has: HEX (34 35 35 30)

F5529 reads: HEX (18 1A 1A 1A)

We tried other lower speed initialization combinations that did not work as well.

Also, remember that MCLK and SMCLK are sourced from XT2 (16MHz)

These 16-MHz/8-MHz initializations DO NOT work:

UCS_initClockSignal(UCS_MCLK,  UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_1);

UCS_initClockSignal(UCS_SMCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_2);

SPI bus is sourced from undivided SMCLK (i.e. SPI bus rate is 8MHz)

Any thoughts here?

These 8-MHz/4-MHz initializations DO NOT work:

UCS_initClockSignal(UCS_MCLK,  UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_2);

UCS_initClockSignal(UCS_SMCLK, UCS_XT2CLK_SELECT, UCS_CLOCK_DIVIDER_4);

SPI bus is sourced from undivided SMCLK (i.e. SPI bus rate is 4MHz)

Any thoughts here?

Additional Reading:

We did some research of the data sheet (SLAS590P, Pages 39 - 41), which discusses USCI (SPI Master Mode) Clock Frequency.

In particular, the sheet mentions fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave));

When utilizing even the smallest (lowest) valued time parameters, we get a tLO/HI of 65nS.

That 65nS tLO/HI gives fUCxCLK =7692307.692 Hz or 7.692MHz.

My question is, does the fUCxCLK determine the maximum SPI bus rate for the MSP430F552x series MCUs?

If fUCxCLK is the SPI bus speed limiting factor then that sheds some light on the 16MHz SPI issues we are seeing. 

Please advise.

Thanks in advance.

Try shorter wires. (Seriously.) I've seen bit-shifting/smearing even at 8MHz over 5-6" wires. Also, try to keep them the same length.

PCB traces are much more accommodating, once you get to that phase of the project.

Hi Bruce

Thanks for your comment!

Hello Xiaodong LI 

Any thoughts on the  fUCxCLK parameter (SLAS590P, Pages 39 - 41), as a SPI bus maximum speed limitation?

Thanks,

You show how you initialize the clock system but not the SPI port. Which would seem to be pretty important when discussing a SPI problem.