MSP430F4794: Protection of SD16_A inputs against negative voltages

Note the Absolute Maximum Ratings:

The most negative voltage is -0.3 V, implying a clamp diode from VSS to the input.

I know this limit. But for analog inputs of SD16_A the absolute limit is different: AVss-1V. Anyway my question is not about the limits, but about internal protection circuit.

Where do you see that? If that is indeed the case, then TI needs to change the Absolute Maximum ratings.

Near the end of p. 47 of the same datasheet:

And our measurement shows there is no clamping near the -1V limit.

So, TI will need to step in and explain the discrepancy. I would guess, that the esd protection for the analog inputs is 3 ESD diodes in series.

We would like such 3-diode protection. The problem is that even -5V provided via resistor (3kOhm) is not clamped on an analog input (Ax.0+). (And it is not a result of chip damage; analog inputs behave this way for each chip piece; and when input signal returns to normal range, the SD16_A works as expected.)

The purpose of the clamping diodes, if present, is to prevent latchup. (CMOS will latch up when the input voltage exceeds the voltages rails enough to trigger a parasitic SCR.) Any ESD protection is secondary.

You can't assume all pins will have these diodes. Pins which have multiple functions including ADC input probably do. A dedicated ADC input perhaps not.

In this case where you know that the input circuit can drive the input pin outside the recommended operating range, you should provide external protection. A current limiting resistor and two clamping diodes.

Thank you. However it seems every chip pin vulnerable to damage by ESD (so also Ax.0+) should have at least basic ESD protection (including negative ESD) - even where the latchup is not a threat.

I have measured on the device for the SD16 input pins also have the protection diodes to AVCC and AVSS.

In which MSP430 device and what was the negative threshold voltage? SD16 is different than SD16_A and individual chip types may have different specs.

I measured with msp430f4794. As you have know the max value is AVss-1V. 

Yes, I know the specified limit. But what negative clamping voltage have you received on A0.x in your measurement?

We have measured several pieces of MSP430F4794 Rev. J, both on the targer PCBs, as well as not assembled, brand new pieces. We can see expected clamping for digital pins  (vs. DVcc and DVss), as well as for positive voltages on analog inputs (vs. AVcc). But I can definitely confirm that we do not see any clamping for negative voltages on A0.x inputs vs. AVss. Even -5V (provided by 3k protecting resistor) IS NOT clamped on these pins. (The chips were delivered by authorized distributor and are otherwise functional.)

Marcin Kocikowski said:

But I can definitely confirm that we do not see any clamping for negative voltages on A0.x inputs vs. AVss

Yes, you are right. When put a voltage at VSS and measure the A0.X  it seems open.

So what is internal protection circuit against negative ESD on Ax.x pins in this chip?

Yes, I think so

Sorry, but this does not answer my question "So WHAT is internal protection circuit against negative ESD on Ax.x pins in this chip?"

Sorry, it seems no negative ESD protection there.