Hello good morning,
I am facing a problem trying to modify the code of someone else. In this case, I am working with a board which allocates a MSP430. This board accept a SPI communication as slave using only 3 wires (MISO, MOSI and SCLK). Now I am trying to implement a "CS" using a very simple approach, which consists in an if sentence inside the SPI ISR that evaluates the value of a GPIO. If the GPIO = 0, then saves the command and goes out the interrupt. However, if the GPIO = 0, the SPI port is configured as input GPIO (if not, the MISO bus is pulled down and is not possible to connect another slave in the same bus). The idea is to re-configure the SPI each time the GPIO = 0 inside the ISR.
I tried to do it, but never is re-configured again. It works only the first time. Then, If I configure the port as input GPIO, I cannot configure it as SPI.
Is it the correct approach? I am missing something else? Is there another way to do it?
Thank you in advance.
Best regards,
Leandro
SPI ISR source code
//USART1RX Interruption Service Routine #pragma CODE_SECTION(SPI1_rx, ".m_3c00_200") #pragma RETAIN(SPI1_rx) #pragma vector = USART1RX_VECTOR __interrupt void SPI1_rx(void) { IE2 &= ~URXIE1; _BIC_SR(GIE); // Disable non-maskable interrupts. if(P5IN & BIT0){ //P5.0 is HIGH P5SEL = 0x0F; // Setup P5 for SPI mode U1CTL = CHAR + SYNC +SWRST; // 8-bit, SPI, Slave U1TCTL = CKPH + CKPL + STC; // 3-wire ME2 = USPIE1; // Module enable U1CTL &= ~SWRST; // SPI enable *arrayInPtr = U1RXBUF; } else{ P5SEL = 0x00; P5DIR = 0xF0; // P5.0 to P5.3 are assigned to SPI1. P5OUT = 0; } commStatus |= INCOMING_BYTE; IE2 |= URXIE1; // Receive interrupt enable _BIS_SR(GIE); // Enable non-maskable interrupts. IFG2 &= ~URXIFG1; // Clear ISR flag. return; }
Function to configure SPI
#pragma CODE_SECTION(turnOnSpi1AsSlave, ".m_3e00_200") #pragma RETAIN(turnOnSpi1AsSlave) void turnOnSpi1AsSlave(void){ P5SEL |= 0x0F; // Setup P5 for SPI mode U1CTL = CHAR + SYNC +SWRST; // 8-bit, SPI, Slave U1TCTL = CKPH + CKPL + STC; // 3-wire ME2 = USPIE1; // Module enable U1CTL &= ~SWRST; // SPI enable IE2 |= URXIE1; // Receive interrupt enable _BIS_SR(GIE); // Enable non-maskable interrupts. return; }