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MSP430F1612: SPI configuration

Part Number: MSP430F1612

Hello good morning,

I am facing a problem trying to modify the code of someone else. In this case, I am working with a board which allocates a MSP430. This board accept a SPI communication as slave using only 3 wires (MISO, MOSI and SCLK). Now I am trying to implement a "CS" using a very simple approach, which consists in an if sentence inside the SPI ISR that evaluates the value of a GPIO. If the GPIO = 0, then saves the command and goes out the interrupt. However, if the GPIO = 0, the SPI port is configured as input GPIO (if not, the MISO bus is pulled down and is not possible to connect another slave in the same bus). The idea is to re-configure the SPI each time the GPIO = 0 inside the ISR.

I tried to do it, but never is re-configured again. It works only the first time. Then, If I configure the port as input GPIO, I cannot configure it as SPI.

Is it the correct approach? I am missing something else? Is there another way to do it?

Thank you in advance.

Best regards,

Leandro

SPI ISR source code

//USART1RX Interruption Service Routine
#pragma CODE_SECTION(SPI1_rx, ".m_3c00_200")
#pragma RETAIN(SPI1_rx)
#pragma vector = USART1RX_VECTOR
__interrupt void SPI1_rx(void) {

    IE2   &= ~URXIE1;
    _BIC_SR(GIE);                   // Disable non-maskable interrupts.

    if(P5IN & BIT0){ //P5.0 is HIGH
        P5SEL  = 0x0F;                 // Setup P5 for SPI mode
        U1CTL   = CHAR + SYNC +SWRST;   // 8-bit, SPI, Slave
        U1TCTL  = CKPH + CKPL + STC;    // 3-wire
        ME2     = USPIE1;               // Module enable
        U1CTL  &= ~SWRST;               // SPI enable

        *arrayInPtr = U1RXBUF;
    }
    else{
        P5SEL = 0x00;
        P5DIR = 0xF0;   // P5.0 to P5.3 are assigned to SPI1.
        P5OUT = 0;
    }
    commStatus |= INCOMING_BYTE;

    IE2    |= URXIE1;               // Receive interrupt enable
    _BIS_SR(GIE);                   // Enable non-maskable interrupts.
    IFG2 &= ~URXIFG1;               // Clear ISR flag.

	return;
}

Function to configure SPI

#pragma CODE_SECTION(turnOnSpi1AsSlave, ".m_3e00_200")
#pragma RETAIN(turnOnSpi1AsSlave)
void turnOnSpi1AsSlave(void){
	P5SEL  |= 0x0F;              	// Setup P5 for SPI mode
	U1CTL   = CHAR + SYNC +SWRST;   // 8-bit, SPI, Slave
	U1TCTL  = CKPH + CKPL + STC; 	// 3-wire
	ME2     = USPIE1;               // Module enable
	U1CTL  &= ~SWRST;               // SPI enable
	IE2    |= URXIE1;               // Receive interrupt enable
	_BIS_SR(GIE); 	    			// Enable non-maskable interrupts.
	return;
}

  • Hi Leandro

    Could you please debug the code by breakpoint? does code can enter the interrupt handling (turnOnSpi1AsSlave) every time you need?

    Thanks!

  • Hello Xiaodong,

    Thank you for your prompt response. Yes, we have debugged it and every time we call that function, the program enters inside it. Maybe it is necessary to implement a delay after configuring it as SPI? I will try it.

    Best regards,

    Leandro

  • Once you disconnect (PSEL) the pins, you won't see another SPI interrupt. The Rx interrupt is too late in any case.

    I think the USART will do most/all of what you want using 4-pin (slave) mode by setting STC=0. [Ref User Guide (SLAU049F) Sec 14.2.3]

  • Hello Bruce,

    Thank you for your advice. However, the hardware is a custom board which only allows SPI communication. I am calling the function turnOnSpi1AsSlave() each time the interrupt finish and turns back to the normal flow of the program.

    Calling that function, I receive a 0xBF, but I am waiting for a 0xFB. Maybe the problem in this case could be the byte order?

    Best Regards,

    Leandro

  • I'm not sure I understand the limitation of the board. Is the master's Chip Select connected to the slave's P5.0(=STE1)? If so, you should be able to use 4-pin mode.

    A particular hazard of trying to implement 4-pin (3-pin + CS) using 3-pin + software is that each time the master asserts /CS (STE1=0) your software needs to recognize this and start up its side of the SPI before the master clocks out its first bit; this could be a very tight race. If the slave comes in mid-transaction (i.e. late), you could see bit-shifting or bit-smearing. (0xFB bit-reversed is 0xDF, so I don't think it's that.)

  • Thank you Bruce! I implemented the 4-pin mode and the froblem was solved.

    Best regards,

    Leandro

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