Other Parts Discussed in Thread: ADS8866, MSPM0G3507
Tool/software:
MSP430FR5994 SPI communication, using a 16MHz clock, when sending one byte followed by the next byte, there is a 6.63µs gap between each byte?
//******************************************************************************
// SPI SRAM I/O Initial *******************************************************
//******************************************************************************
void SPI_IO_SRAM_initial(void)
{
// Configure SPI
P6SEL0 |= BIT4 | BIT5 | BIT6;
P6SEL1 &= ~(BIT4 | BIT5 | BIT6);
SLAVE_SRAM_CS_DIR |= SLAVE_SRAM_CS_PIN;
SLAVE_SRAM_CS_OUT |= SLAVE_SRAM_CS_PIN;
}
//******************************************************************************
// SPI SRAM register Initial *************************************************
//******************************************************************************
void SPI_register_SRAM_initial(void)
{
//Clock Polarity: The inactive state is high
//MSB First, 8-bit, Master, 3-pin mode, Synchronous
UCB3CTLW0 = UCSWRST; // **Put state machine in reset**
UCB3CTLW0 |= ( UCCKPH | UCMSB | UCSYNC =// V: UCCKPH ; VV UCCKPL ; V ~UCCKPL & ~UCCKPH ;
| UCMST | UCSSEL__SMCLK ); // 3-pin, 8-bit SPI Slave
UCB3BRW = 0x00; //0x20
// UCMCTLW = 0;
UCB3CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
UCB3IE |= UCRXIE; // Enable USCI0 RX interrupt
}
//******************************************************************************
// SPI_SRAM_Master_Write_data *************************************************
//******************************************************************************
void SPI_SRAM_Master_Write_data(uint32_t Write_SRAM_start_Address,uint8_t *data_buf ,uint16_t Write_SRAM_len)
{
uint16_t i= 0;
SRAM_MasterMode = SRAM_TX_DATA_MODE;
SRAM_ReceiveIndex = 0;
SRAM_RXByteCtr = 0;
SRAM_TransmitIndex = 0;
SRAM_TXByteCtr = (SRAM_Instruction_len + SRAM_Address_len + Write_SRAM_len); // Total SRAM_TransmitIndex length.
SRAM_TransmitBuffer[0] = 0x02; // SEQUENTIAL WRITE (SPI MODE)
//Read address 3 byte.
SRAM_TransmitBuffer[1] = ((Write_SRAM_start_Address >> 16) & 0xFF); // Address h byte.
SRAM_TransmitBuffer[2] = ((Write_SRAM_start_Address >> 8) & 0xFF); // Address m byte.
SRAM_TransmitBuffer[3] = (Write_SRAM_start_Address & 0xFF); // Address l byte.
for(i= 0; i < Write_SRAM_len; i++)
{
SRAM_TransmitBuffer[4+i] = data_buf[i];
}
SLAVE_SRAM_CS_OUT &= ~(SLAVE_SRAM_CS_PIN);
UCB3TXBUF = SRAM_TransmitBuffer[SRAM_TransmitIndex++]; //Send first to start.
SRAM_Processing_falg = 1;
__bis_SR_register(/*CPUOFF + */GIE); // Enter LPM0 w/ interrupts
while(SRAM_Processing_falg);
SLAVE_SRAM_CS_OUT |= SLAVE_SRAM_CS_PIN;
}
//******************************************************************************
// SPI SRAM SendUCB1Data *****************************************************
//******************************************************************************
void SendUCB3Data(uint8_t val)
{
while (!(UCB3IFG & UCTXIFG)); // USCI_B3 TX buffer ready?
UCB3TXBUF = val;
}
//******************************************************************************
// SPI USCI_B3_VECTOR Interrupt ***********************************************
//******************************************************************************
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_B3_VECTOR
__interrupt void USCI_B3_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B3_VECTOR))) USCI_B3_ISR (void)
#else
#error Compiler not supported!
#endif
{
uint8_t ucB3_rx_val = 0;
switch(__even_in_range(UCB3IV, USCI_SPI_UCTXIFG))
{
case USCI_NONE: break;
case USCI_SPI_UCRXIFG: //SPI Rx interrupt
ucB3_rx_val = UCB3RXBUF;
UCB3IFG &= ~UCRXIFG;
switch (SRAM_MasterMode)
{
case SRAM_TX_REG_ADDRESS_MODE:
{
__no_operation();
}
break;
case SRAM_TX_DATA_MODE:
{
if (SRAM_TransmitIndex < SRAM_TXByteCtr)
SendUCB3Data(SRAM_TransmitBuffer[SRAM_TransmitIndex++]);
else
{
SRAM_MasterMode = SRAM_IDLE_MODE;
// __bic_SR_register_on_exit(CPUOFF); // Exit LPM0
SRAM_Processing_falg = 0;
}
__no_operation();
}
break;
case SRAM_RX_DATA_MODE:
{
__no_operation();
}
break;
case SRAM_TX_RECEIVE_DATA_SEND_MODE:
{
if (SRAM_TransmitIndex < SRAM_TXByteCtr)
SendUCB3Data(SRAM_TransmitBuffer[SRAM_TransmitIndex++]);
else
{
SRAM_MasterMode = SRAM_TX_RECEIVE_DATA_REC_MODE;
SendUCB3Data(DUMMY);
}
__no_operation();
}
break;
case SRAM_TX_RECEIVE_DATA_REC_MODE:
{
if (SRAM_RXByteCtr){
SRAM_rec_data_buffer[SRAM_ReceiveIndex++] = ucB3_rx_val;
//Transmit a dummy
SRAM_RXByteCtr--;
}
if (SRAM_RXByteCtr == 0){
SRAM_MasterMode = SRAM_IDLE_MODE;
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
else{
SendUCB3Data(DUMMY);
}
}
break;
default:
__no_operation();
break;
}
break;
case USCI_SPI_UCTXIFG: //SPI Tx interrupt
{
}
break;
}
}
