MSP430F67791: SMCLK Value and EVM430F6779 Manual

By default, MCLK_DEF = 16, so I don't know what value the mode is set to in this snippet:
#else

unsigned int d, dco_div_bits;
unsigned int mode = 0;

// save current state of FLL loop control
unsigned short globalInterruptState = __get_SR_register() & SCG0;
__bic_SR_register(SCG0); // Disable FLL loop control

d = ratio;
dco_div_bits = FLLD__2; // Have at least a divider of 2
if (fsystem > 16000){
d >>= 1 ;
mode = 1;
}
else
fsystem <<= 1; // fsystem = fsystem * 2

while (d > 512)
{
dco_div_bits = dco_div_bits + FLLD0; // set next higher div level
d >>= 1;
}

UCSCTL0 = 0x000; // Set DCO to lowest Tap

UCSCTL2 &= ~(0x3FF); // Reset FN bits
UCSCTL2 = dco_div_bits | (d - 1);

if (fsystem <= 630) // fsystem < 0.63MHz
UCSCTL1= DCORSEL_0 ;
else if (fsystem < 1250) // 0.63MHz < fsystem < 1.25MHz
UCSCTL1= DCORSEL_1 ;
else if (fsystem < 2500) // 1.25MHz < fsystem < 2.5MHz
UCSCTL1= DCORSEL_2 ;
else if (fsystem < 5000) // 2.5MHz < fsystem < 5MHz
UCSCTL1= DCORSEL_3 ;
else if (fsystem < 10000) // 5MHz < fsystem < 10MHz
UCSCTL1= DCORSEL_4 ;
else if (fsystem < 20000) // 10MHz < fsystem < 20MHz
UCSCTL1= DCORSEL_5 ;
else if (fsystem < 40000) // 20MHz < fsystem < 40MHz
UCSCTL1= DCORSEL_6 ;
else
UCSCTL1= DCORSEL_7 ;

while (SFRIFG1 & OFIFG) { // check OFIFG fault flag
UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC flute Flags
SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}

if (mode == 1) // fsystem > 16000
SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK); // select DCOCLK
else
SELECT_MCLK_SMCLK(SELM__DCOCLKDIV + SELS__DCOCLKDIV); // select DCODIVCLK

__bis_SR_register(globalInterruptState); // restore previous state
#endif

However, I understand that finally, SMCLK takes in this case the frequency of DCOCLK or DCOCLKDIV, since according to slau390f:
SMCLK: Subsystem master clock. SMCLK is software-selectable as XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and, when available, XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32 within the FLL block. SMCLK can be divided by 1, 2, 4, 8, 16, or 32. SMCLK is software-selectable by individual peripheral modules.

I have two specific questions:
1. What frequency does SMCLK use and what is its value?
2. What is the maximum value I can assign to it and how?

I look forward to any responses. Thank you.

- Juan Arboleda

Hi Juan,

If using MSP430F67xx for energy measurement, you can refer to MSP-EM-DESIGN-CENTER MSP-EM-DESIGN-CENTER

And you can find a User Guide in the page, Energy Measurement Technology Guide, It provide some SMCLK frequency options, hope it would be helpful to you.

Best Regards,
Peter