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ADC VARIATION IN MSP430F155

Other Parts Discussed in Thread: MSP430F155

                                 hi all am using msp430f155 controller for my project.. and i tried to do a adc and outed in dac.here i used external referencre 3v for adc and dac..here below its my code....and i try to check the adc value by outing the first channel ADC  value directly to the DAC.. and i put the break point at the end of the program. and i monitored the a1 chanel decimal value for my adc input..

here my input voltage is  =1.060V  for this input the Nadc should be  =1449..but if  i watching  at break point  am getting .1439,1452,1463 like that so each time while i excute am getting 15 to 20 value difference because of this am getting error about 4mv in dac output.. how can i minimize this error..and i need to know the reason for this..






#include <msp430x15x.h>

#define Num_of_Results 10

static unsigned int A0results[Num_of_Results]; // These need to be global in
static unsigned int A1results[Num_of_Results]; // this example. Otherwise, the
static unsigned int A2results[Num_of_Results]; // compiler removes them because
static unsigned int A3results[Num_of_Results]; // they are not used
static unsigned int A4results[Num_of_Results]; // they are not used
static unsigned int Arefresults[Num_of_Results]; // they are not used
unsigned int A0 = 0,A1 = 0,A2 = 0,A3 = 0,A4=0,AA0 = 0,AA1= 0,AA2 = 0,AA3 = 0,AA4=0;
unsigned int index = 0,AVG = 0,AAref=0,i,Aref=0;
void main(void)
{

WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer

BCSCTL1 |= XTS;
do
{
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFF; i > 0; i--); // Time for flag to set
}
while ((IFG1 & OFIFG)); // OSCFault flag still set?

BCSCTL2 |= SELM_3+SELS+DIVM_0; // MCLK= LFXT1



P6SEL = 0x2F; // Enable A/D channel inputs
ADC12CTL0 = ADC12ON+MSC+SHT0_8; // Turn on ADC12, extend sampling time
ADC12CTL1 = ADC12SSEL_1+SHP+CONSEQ_3; // Use sampling timer, repeated sequence
ADC12MCTL0 = INCH_0+SREF_2; // EXTERNAL ref, channel = A0
ADC12MCTL1 = INCH_1+SREF_2; // EXTERNAL ref, channel = A1
ADC12MCTL2 = INCH_2+SREF_2; // EXTERNAL ref, channel = A2
ADC12MCTL3 = INCH_3+SREF_2; // EXTERNAL ref, channel = A3
ADC12MCTL4 = INCH_4+SREF_2; // EXTERNAL ref, channel = A4,
ADC12MCTL5 = INCH_5+SREF_2+EOS; // EXTERNAL ref, channel = A5,end seq
ADC12CTL0 |= ENC; // Enable conversions
ADC12CTL0 |= ADC12SC; // Start conversions

while(1)
{
while ((ADC12IFG & BIT0)==0);

for(index=0;index < Num_of_Results;index++) //code from reading from res and adding the 5 analog inputs
{

A0results[index] = ADC12MEM0; // Move A0 results, IFG is cleared
A0=A0+A0results[index];

A1results[index] = ADC12MEM1; // Move A1 results, IFG is cleared
A1=A1+A1results[index];

A2results[index] = ADC12MEM2; // Move A2 results, IFG is cleared
A2=A2+A2results[index];

A3results[index] = ADC12MEM3; // Move A3 results, IFG is cleared
A3=A3+A3results[index];

A4results[index] = ADC12MEM4; // Move A4 results, IFG is cleared
A4=A4+A4results[index];

Arefresults[index] = ADC12MEM5; // Move A5 results, IFG is cleared
Aref=Aref+Arefresults[index];
}
AA0= A0/Num_of_Results;
AA1= A1/Num_of_Results;
AA2= A2/Num_of_Results;
AA3= A3/Num_of_Results;
AA4= A4/Num_of_Results;
AAref= Aref/Num_of_Results;

A0 = 0;
A1 = 0;
A2 = 0;
A3 = 0;
A4 = 0;
Aref = 0;



AVG = (AA0+AA1+AA2+AA3+AA4)/5;
DAC12_1CTL = DAC12SREF_2+DAC12AMP_7 + DAC12ENC+DAC12IR; // external ref gain 1
DAC12_1DAT = AA0;//AVG;

A0 = 0; //am putting break point here
A1 = 0;
A2 = 0;
A3 = 0;
A4 = 0;
// P1OUT = 0x00;

}
}
  • Hello,

    since your error occurs while running the adc already, first thing I think of, how stable are your signals and how stable is your power supply and your Vref? Are all decoupling capacitors for AV and DV in place and properly close to the MSP? Since you are reading values above as well as values below your estimated target I would first think of noise on one of the voltages.

    Also an error of 15 in ADC12MEM would result in 10.99mV error not just 4mV.

  • my input and Vref are in stable condition only and by refering the data sheet i  puted the decoupling capacitor and capacitor across Vref properely here am tabulating my error below for different voltage after putting capacitor across Vref and gnd

    ADC INPUT DAC OUTPUT ERROR
    0.127 0.128 -0.001
    0.646 0.645 0.001
    1.175 1.172 0.003
    1.698 1.693 0.005
    2.239 2.233 0.006
  • You don't set any SHTx values. So you provide only 4 ADC12CLK cycles (<1µs) for sampling the input signal. That's quite low. With such a short sampling time, the sampling capacitor hasn't enough tiem to charge through the ~1k input resistance. And teh resutl will be lower than expected. On a high-impedance signal source, the results would differ even more.

    Independent of this, there is a small offset and gain error on both, ADC and DAC. Unless these errors are identical on both 8not likely), you will experience a small difference too. You might be able to calibrate this away (2-point calibration of both, and lots of math, which can be done mostly at compile-time, if the formula is properly done with fixed-point integer arithmetics)

  • so waht can i do now to recitify this error.. whether bY means of extending the ADC12CLK cycles.and kindly say me the what will be the safest SHTx value.

  • There will be no safest value for SHTx - it depends on your application.

    The sample time depends on SHTx (4,8,16,32,64 cycles), the ADC10DIVx (prescaler) and ADC10SSELx. If your input is static a large sample time might be appropriate but if you want capture audio for example you will need a smaller sample time so that your signal is not smoothed out of existence. In contrast if you have a signal with some noise (ripple from a switch mode power supply) and want to measure the median the sample and hold time should be a multiple of the (expected) noise frequency. 

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