How to link MSP430F2013 USB type to Hyper terminal? The process to as minimal as possible.
Pls reply..
Rgds,
Hi, Andy!
I'm glad indeed to see your answer and wise questions. Sorry for late responce :-).
I've download example slave code of msp430x20x3_usi_15.c (by R. B. Elliott / H. Grewal demo) from
slac080i.zip into my MSP430F2013 (68K _G_4_EENR_ver.B)
and check with another (linked with first one by I2C) MSP430F2013 (68K _G_4_EENR_ver.B), downloaded
with example Master code of msp430x20x3_usi_12.c (by R. B. Elliott / H. Grewal demo) from
slac080i.zip. The only change was using #include <msp430x20x3.h> instead of #include <msp430x20x2.h>
Then, using oscilloscope, I saw data traffic was correct.
So, I added to this I2C net one MSP430F5509 and loaded it with example code
MSP430F550x_uscib0_i2c_09.c (after D. Archbold/B.Nisarga) from slac394c.zip
Changes were
1) #include <msp430f5509.h> instead of #include <msp430f5510.h>
2) Slave address 0x44 instead of 0x48(rezerved for the first slave MSP430F2013)
And again, I saw perfect data traffic now between 2013 and 5509.
At last, I took the C1_Example from MSP430_USB_API_Stacks directory of
MSP430USBDevelopersPackage_3_20_02.zip packet as the base for I2C-USB bridge application and made a
fusion into question_to_Andy.c code. The file with it ia attached to this post.
Enumeration was successful. Virtual COM5 was established and connected to X-CTU terminal software.
After successful compilation, linking, downloading and debugging start I've traced writing of the
first byte 0x5F to SRL register (5F_the_first_byte.JPG),
then I've traced second byte (0x60_the_2nd_byte.JPG)
third byte (0xDD_the_last_5th_byte.JPG)
fourth byte (0xD1_the_last_5th_byte.JPG)
and last fifth byte (0x33_the_last_5th_byte.JPG)
For other 5-bytes pachage X-CTU terminal shows 3 "spoiled" bytes (7F_7F_29_7F_33.JPG).
To say truth, sometimes there is only one spoiled out of 5 bytes (64_65_17_7F_33.jpg).
IMHO, the "spoiling" occurs after data loading in USISRL register and before it's shifting onto Data line of I2C. I suppose, oscilloscope's pictures can provide evidence and aliby for 5509 bridge(Spoiled_bytes_I2C.JPG).
Hope, all details was elucidated.
Thanks a lot for your interest, Andy.
All comments will be appreciated.
Best regards,
Vlad Sukharev
//******************************************************************************
// MSP430F2013 - I2C Master Transmitter / Reciever, multiple bytes
//
// Description: I2C Master communicates with I2C Slave using
// the USI. Master data should be 0x55 for the first two bytes
// then two bytes from ADC and CS for 4 bytes
// ACLK = n/a, MCLK = SMCLK = Calibrated 1MHz
//
// ***THIS IS THE MASTER CODE***
//
// Slave (0x44) Master Slave (0x48)
// (msp430x5509_usi_15.c) (msp430x20x3_usi_15.c)
// (MSP430F550x_uscib0_i2c_09.c)
// MSP430F5509 0x44 MSP430F2013 MSP430F2013
// ----------------- ----------------- -----------------
// /|\| XIN|- /|\| XIN|- /|\| XIN|-
// | | | | | | | | |
// --|RST XOUT|- --|RST XOUT|- --|RST XOUT|-
// | | | | | |
// <-|P1.0 | | | | |
// | | | P1.0|-> | P1.0|->
// | SDA/P4.2|<-----|P1.6/SDA <-------+-------|P1.6/SDA |
// | SCL/P4.1|<-----|P1.7/SCL --------+------>|P1.7/SCL |
//
// Note: internal pull-ups are used in this example for SDA & SCL
//
// R. B. Elliott / H. Grewal / V.Sukharev
// Texas Instruments Inc.
// April 2013
// Built with IAR Embedded Workbench Version: 5.40.1
//******************************************************************************
#include <msp430x20x3.h>
#define number_of_bytes 5 // How many bytes?
unsigned short volatile Res=0, ndx = 0;
void Master_Transmit(void);
void Master_Recieve(void);
void Setup_USI_Master_TX(void);
void Setup_USI_Master_RX(void);
const unsigned short volatile SLV_Data = 0xD125;
unsigned char volatile MST_Data[10]; // Variable for transmitted data
char SLV_Addr = 0x88;
int I2C_State, tin, Bytecount, Transmit = 0; // State variable
int Packet_ind = 0;
void Data_TX (void);
void Data_RX (void);
void main(void)
{
volatile unsigned int i; // Use volatile to prevent removal
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog
//unsigned long longAcc = 0;
if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF)
{ // If calibration constants erased
while(1); // do not load, trap CPU!!
}
BCSCTL1 = CALBC1_1MHZ; //RSEL2 + RSEL3;// // BCSCTL2 |= DIVS_3; // SMCLK/8
DCOCTL = CALDCO_1MHZ; //DCO2+MOD0+MOD1+MOD4;// // Set DCO
P1OUT = 0xC0;
P1REN |= 0xC0; // P1.6 & P1.7 Pullups
P1DIR = 0xFF; // Unused pins as outputs
P2OUT = 0;
P2DIR = 0xFF;
for (i = 0; i < 10000; i++); // Delay for MCLC to stabilize
Master_Recieve();
SD16CTL = SD16REFON + SD16SSEL_1 + SD16DIV_3 //SMCLK
+ SD16XDIV_0 + SD16VMIDON; // �� 819200 Hz
SD16CCTL0 |= SD16OSR_256 + SD16IE; // Enable interrupt, OSR=256,
SD16INCTL0 = SD16INCH_6; // A6+/- //SD16INCTL0 = SD16INCH_1; // A1+/-
SD16CCTL0 |= SD16SC; // SD16 START
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 with interrupt
SD16CCTL0 &= ~SD16IE; // disable interrupts from ADC
MST_Data[2] = Res;
MST_Data[3] = Res >> 8;
MST_Data[4] = 0x33;
for (i = 0; i < 50000; i++); // Delay for Data to stabilize
Master_Transmit(); // Set flag and start communication
}
//__interrupt void watchdog_timer(void)
#pragma vector=SD16_VECTOR
__interrupt void SD16ISR(void) {
switch (SD16IV) {
case 2: // SD16MEM Overflow
break;
case 4: // SD16MEM0 IFG
Res = SD16MEM0; // Save result (clears IFG)
break; }
__bic_SR_register_on_exit(CPUOFF); }
/******************************************************
// USI interrupt service routine
// Data Transmit : state 0 -> 2 -> 4 -> 10 -> 12 -> 14
// Data Recieve : state 0 -> 2 -> 4 -> 6 -> 8 -> 14
******************************************************/
#pragma vector = USI_VECTOR
__interrupt void USI_TXRX (void)
{
switch(__even_in_range(I2C_State,14))
{
case 0: // Generate Start Condition & send address to slave
P1OUT |= 0x01; // LED on: sequence start
Bytecount = 0;
USISRL = 0x00; // Generate Start Condition...
USICTL0 |= USIGE+USIOE;
USICTL0 &= ~USIGE;
if (Transmit == 1){
USISRL = 0x88; // Address is 0x44 << 1 bit + 0 (rw)
}
if (Transmit == 0){
USISRL = 0x91; // 0x91 Address is 0x48 << 1 bit
// + 1 for Read
}
USICNT = (USICNT & 0xE0) + 0x08; // Bit counter = 8, TX Address
I2C_State = 2; // next state: rcv address (N)Ack
break;
case 2: // Receive Address Ack/Nack bit
USICTL0 &= ~USIOE; // SDA = input
USICNT |= 0x01; // Bit counter=1, receive (N)Ack bit
I2C_State = 4; // Go to next state: check (N)Ack
break;
case 4: // Process Address Ack/Nack & handle data TX
if(Transmit == 1){
USICTL0 |= USIOE; // SDA = output
if (USISRL & 0x01) // If Nack received...
{ // Send stop...
USISRL = 0x00;
USICNT |= 0x01; // Bit counter=1, SCL high, SDA low
I2C_State = 14; // Go to next state: generate Stop
P1OUT |= 0x01; // LED on: error
}
else
{ // Ack received, TX data to slave...
USISRL = MST_Data[0]; // Load first data byte
for (int i = 0; i < 1; i++); USICNT |= 0x08;// Bit counter = 8, start TX
I2C_State = 10; // next state: receive data (N)Ack
P1OUT &= ~0x01; // Turn off LED
Bytecount++;
break;
}
} if(Transmit == 0){
if (USISRL & 0x01) // If Nack received
{ // Prep Stop Condition
USICTL0 |= USIOE;
USISRL = 0x00;
USICNT |= 0x01; // Bit counter= 1, SCL high, SDA low
I2C_State = 8; // Go to next state: generate Stop
P1OUT |= 0x01; // Turn on LED: error
}
else{ Data_RX();} // Ack received
}
break;
case 6: // Send Data Ack/Nack bit
USICTL0 |= USIOE; // SDA = output
if (Bytecount <= number_of_bytes-2)
{ // If this is not the last byte
if (Bytecount < 2) MST_Data[Bytecount] = USISRL;
USISRL = 0x00; // Send Ack
P1OUT &= ~0x01; // LED off
I2C_State = 4; // Go to next state: data/rcv again
Bytecount++;
}
else //last byte: send NACK
{
USISRL = 0xFF; // Send NAck
P1OUT |= 0x01; // LED on: end of comm
I2C_State = 8; // stop condition
}
USICNT |= 0x01; // Bit counter = 1, send (N)Ack bit
break;
case 8: // Prep Stop Condition
USICTL0 |= USIOE; // SDA = output
USISRL = 0x00;
USICNT |= 0x01; // Bit counter= 1, SCL high, SDA low
I2C_State = 14; // Go to next state: generate Stop
break;
case 10: // Receive Data Ack/Nack bit
USICTL0 &= ~USIOE; // SDA = input
USICNT |= 0x01; // Bit counter = 1, receive (N)Ack bit
I2C_State = 12; // Go to next state: check (N)Ack
break;
case 12: // Process Data Ack/Nack & send Stop
USICTL0 |= USIOE;
if (Bytecount == number_of_bytes){// If last byte
USISRL = 0x00;
I2C_State = 14; // Go to next state: generate Stop
P1OUT |= 0x01;
USICNT |= 0x01; } // set count=1 to trigger next state
else{
P1OUT &= ~0x01; // Turn off LED
Data_TX();
}
break;
case 14:// Generate Stop Condition
USISRL = 0xFF; // USISRL = 1 to release SDA
USICTL0 |= USIGE; // Transparent latch enabled
USICTL0 &= ~(USIGE+USIOE); // Latch/SDA output disabled
I2C_State = 0; // Reset state machine for next xmt
LPM0_EXIT; // Exit active for next transfer
break;
}
USICTL1 &= ~USIIFG; // Clear pending flag
}
void Data_TX (void){
USISRL = MST_Data[Bytecount++]; // Load data byte
USICNT |= 0x08; // Bit counter = 8, start TX
I2C_State = 10; // next state: receive data (N)Ack
}
void Data_RX (void){
USICTL0 &= ~USIOE; // SDA = input --> redundant
USICNT |= 0x08; // Bit counter = 8, RX data
I2C_State = 6; // Next state: Test data and (N)Ack
P1OUT &= ~0x01; // LED off
}
void Setup_USI_Master_TX (void)
{
_DINT();
Bytecount = 0;
Transmit = 1;
USICTL0 = USIPE6+USIPE7+USIMST+USISWRST; // Port & USI mode setup
USICTL1 = USII2C+USIIE; // Enable I2C mode & USI interrupt
USICKCTL = USIDIV_7+USISSEL_2+USICKPL; // USI clk: SCL = SMCLK/128
USICNT |= USIIFGCC; // Disable automatic clear control
USICTL0 &= ~USISWRST; // Enable USI
USICTL1 &= ~USIIFG; // Clear pending flag
_EINT();
}
void Setup_USI_Master_RX (void)
{
_DINT();
Bytecount = 0;
Transmit = 0;
USICTL0 = USIPE6+USIPE7+USIMST+USISWRST; // Port & USI mode setup
USICTL1 = USII2C+USIIE; // Enable I2C mode & USI interrupt
USICKCTL = USIDIV_7+USISSEL_2+USICKPL; // USI clks: SCL = SMCLK/128
USICNT |= USIIFGCC; // Disable automatic clear control
USICTL0 &= ~USISWRST; // Enable USI
USICTL1 &= ~USIIFG; // Clear pending flag
_EINT();
}
void Master_Transmit(void){
Setup_USI_Master_TX();
USICTL1 |= USIIFG; // Set flag and start communication
LPM0; // CPU off, await USI interrupt
for (int i = 0; i < 5000; i++); // Delay between comm cycles
}
void Master_Recieve(void){
Setup_USI_Master_RX();
USICTL1 |= USIIFG; // Set flag and start communication
LPM0; // CPU off, await USI interrupt
for (int i = 0; i < 5000; i++); // Delay between comm cycles
}
Mostly 3rd and 4th byte in package were spoiled. Here its should be 0xAD and 0xD2, respectively.
Oscillopictures downleft shows perfect transfer from slave 2013 to master 2013, so spoiling process, probably, concentrate in software bug into master 2013.
**Attention** This is a public forum