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MSP430FG439 System Clock FLL+ System Clock questions

Jonathan Roberts95043
Prodigy 110 points
Other Parts Discussed in Thread: MSP430FG439

Hi,

I have been trying to figure out what my MCU (MSP430FG439) System clock is running at so that I know how to change the clock speed for USART. Reading from MSP430FG43x.pdf I saw that the system clock is dependent on the value of Vcc, so I am at 3.0 V for the MCU and it should be at 6.41MHz. 

Note: using no external clock source. http://www.ti.com/litv/pdf/slau056j (MSP430FG439) , http://www.ti.com/litv/pdf/slau056j (MSP430X4XX Family )

I scoped a pin for SMCLK and MCLK, for default values i got 285.2kHz. Below are equations for fDCOCLK, for default DCOPLUS is 0.

DCOPLUS = 0: fDCOCLK = (N + 1) x fCLK
DCOPLUS = 1: fDCOCLK = D x (N + 1) x fCLK

N=31,So calculating fCLK, I got 17825Hz. Is this right? I thought it'd be 6.61MHz (fDCOCLK with 1 division 570400Hz)

Below are default values of register when I looked in debug mode.

SCFQCTL
0x1F = 0001 1111 Modulation N=31

SCFI1
0x00 = 0000 0000

ScFI0
0x40 = 0100 0000 FLLD divider loop by 2, No DCO Range, 0.65-6.1MhZ

FLL_CTL0
0x03 = 0000 0011 DCO output is divided BIT7 =0;
XTS_FLL Low freq mode BIT6 = 0;
XCAPxPF 8pF BIT5 =1 , BIT4 = 0;
XT2OF NO fault XT2 oscillator BIT3 = 0;
XT1OF No fault cond LFXT1 BIT2 = 0;
LFOF LFXT No fault cond BIT1 = 0;
DCOF DCO no fault cond BIT0 = 0;

FLL_CTL1

 0x20 = 0010 0000 LFXT1DIG Crystal Input Selected BIT7 = 0;
SMCLKOFF is ON, BIT6 = 0;
XT2OFF is OFF BIT5=1;
SELMx DCOCLK = 00;
SELS DCOCLK BIT2 = 0;
FLL_DIVx divide by 1 , BITS1/1 = 00

I also tried using FN_2 instead to increase the frequency, I get a fDCOCLK to be 1.2MHz with division of 1, and N = 31, which meant that fClock would be 37500Hz. 

Why is the fClock different from the previous case of default values and also, ccs5 says FN_2 range is 1.4MHz - 16MHz, while mine is running at 1.2MHz?

WDTCTL = WDTPW + WDTHOLD; // Stop WDT
SCFI0 |= FN_2;
SCFI0 &= ~BIT6;
SCFI0 |= BIT7; // division of 4 = 300kHz

  • 0
    Guru 227245 points

    Jonathan Roberts95043 said:
    I saw that the system clock is dependent on the value of Vcc

    No. The maximum allowed system clock depends on VCC. Because teh CPU requires a certain voltage to work stable on a given frequency. It can, however, work slower.
    The system frequency is controlled by software. The default frequency is so that it will be slow enough for the overall minimum operating voltage. It is up to you to raise it once a sufficient high voltage is applied.

    Your calculation on fCLK is void. The FLL requires a watch crystal attached to the MSP (32768Hz). If no crystal is attached, fCLK is 0Hz. However, the FLL can adjust the DCO only within its currently selected range, which in your case starts with 285kHz.(see datasheet for the typical and minimal DCO frequencies - the users guide 'range' info is 'averaged' across all 4x family MSPs.

    However, you write that DCOF is clear. But when SCFI1 is zero, DCOF must be set. (see users guide description of what DCO 'fault' means)

    I suggest re-reading chapter 5 of the users guide. Including a closer look at the clock system schematics.

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