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Very slow rising Vcc and BOR

A long time ago in pre-F15x days, I experienced lots of brownout problems. I have not seen that myself since F15x implemented BOR circuit. But recently, I keep hearing from other users reporting problems that seem to be related to brownout for F2xx chips that do have BOR circuit.

I do not know if those reported problems are caused by inadequacies in the BOR. I start to experiment with what I have. Here is a report of what I learned so far. And I am still working on this.

I know that fast changes in Vcc can cause problems. But those problems are hard to investigate and easy to avoid. Thus I only tried with very slowly changing Vcc. Specifically; I use the ADC12 of a F169 to produce a voltage anywhere from 0 to 2.5V in increments of 0.61mV. This ADC12 output is used as the Vcc of other MSP430 chips under investigation.

The first thing I tried is a F135 (which does not have BOR). When I ramp up Vcc slowly, I found that the F135 starts to run at 1.09V. The DCO frequency is very slow (~1Hz) and erratic at that Vcc. It should be about 800kHz and used for MCLK and SMCLK by default. The CPU seems to be able to execute at least a few instructions that are stored in Flash. But I am not sure if it might crash or not.

Next, I tried with a F2471 (which does have BOR). It starts to run at 1.53V instead. DCO frequency is about 1.1MHz (very close to what it should be). And the CPU seems to be able to execute at least a few instructions that are stored in Flash.

BTW, a lot of the code examples and Applications published by TI raise the clock rate right out of reset. If I do that, quite understandably, both F135 and F2471 crash after a few instructions.

So, based on my experiments of a single F135 and a single F2471, the BOR seems to help. But, a few questions emerged:

(1) The data-sheet says I need min 1.8V to run at 4.15MHz. But it does not say what min Vcc voltage is needed to run at 1.1MHz. Is my F2471 safe when Vcc is between 1.53V and 1.8V with MCLK=SMCLK=~1.1MHz?

(2) The data-sheet says at max 1.71V+210mV=1.92V, the BOR will release the reset. There is no min or tpy value. My F2471 did it at 1.52V.  Will other chips with BOR circuit release reset at even lower voltage? (Because there is no min value specified.) If so, is it safe at that even lower voltage?

(3) The data-sheet says below 0.7*1.71V=1.20V the BOR circuit may not do anything. It does not say what the DCO and CPU will do at such voltage. My F135 does funny things at 1.09V Will other chips with BOR circuit start to do funny things before BOR circuit start to take control?

  • Nice write-up.  Just adding some observations here, FWIW:

    It is suspected brown-out issues on the 'F135 that prompted me to look into flash protection strategies, as discussed here:  http://e2e.ti.com/forums/t/8600.aspx

    The 'F135 (which has no BOR) requires that Vcc rise/fall times be faster than +/- 1 V/ms.   [See notes 1 and 2 under PUC/POR in the datasheet.) 

    The 'F235 (which has a BOR) is tested with rise times slower than 3 V/s (.003 V/ms).  [See POR/brownout reset (BOR) and notes in the datasheet.)

    Seems like using the SVS could alleviate some of the spec ambiguities pointed out in O_C_Y's post above, but its current consumption may be unacceptable for low-power apps.  At any rate, the 2x family and beyond do make for more robust systems.

  • Hello,

    Just adding my two cents to your discussion:

    old_cow_yellow said:
    (1) The data-sheet says I need min 1.8V to run at 4.15MHz. But it does not say what min Vcc voltage is needed to run at 1.1MHz. Is my F2471 safe when Vcc is between 1.53V and 1.8V with MCLK=SMCLK=~1.1MHz?

    Yes, any MSP430 device with a BOR circuitry does what it is meant to do: Protect the part by holding it in reset in case of a brownout. The BOR circuitry however is not fine tuned to trigger at 1.799xxxV and has some tolerance associated with it. This ofcourse presents us with the question: what if I am just at that gap in spec?

    Consider a case where the BOR releases early e.g. at 1.6V; the part is rated to work only from 1.8V onwards...In this case code execution will proceed as expected provided MCLK stays at the default DCO.  This is also mentioned in a note in the D/s:

    "During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default DCO settings must not be changed until VCC ≥ VCC(MIN), where VCC(min) is the minimum supply voltage for the desired operating frequency."

    However any peripheral operation is continegent on the D/s specs for e.g. min. Vcc for the ADC module is 2.2V.

    Regards,

    Priya

     

  • Future Readers,

    I just posted a discussion about the BOR and common issues here: http://e2e.ti.com/support/microcontrollers/msp43016-bit_ultra-low_power_mcus/f/166/t/215263.aspx 

     

    Everytime I searched BOR, this post popped up.  Thanks for the useful information Priya!

    Thanks,

    JD

  • JD,

    I have seen suggestions to use a bigger capacitor from nRST to ground. Supposedly the RC delay of nRST rising time can mitigate the problem caused by slow rising of Vcc. I personally do not think this helps. (This capacitor will also impede SBW operation, but that is not the reason of my objection.)

    I have used a scheme for system with slowly rising Vcc. After reset, the first thing I do is to change DCO RSEL to 0. Next I check the reason of reset, if it is caused by BOR or power up, I use LPM0 to wait for the WDT to reset the system. Only when the reset caused by WDT happens, I will run the normal code. This scheme uses very slow DCO to execute very few instructions to add delays.

    Any comments about the above two methods?

    -- OCY

  • Hey OCY,

    I understand the point of the bigger capacitor, but I don't think this would help that much, and could potentially cause other issues, like upon programming. 

    The WDT time solution would help, but even it's going to have limitations.  Basically, your just adding a time delay upon power up.  Since this thread is about Slow VCC rise times, I think this is a fine solution, assuming that after that delay, VCC has reached an acceptable level. 

    There will be certain applications, such as things on battery power, where this assumption might not always be vaild.  Say, the batteries are almost dead, and your MSP is only getting 1.75 V.  In this case, the delay wouldn't fix anything.  In this situation, additional hardware would be necessary.  Either a built in or external SVS.  Or Even a boost converter.

    I slightly mentioned the issue in my write-up, but I had a recent issue when VCC was falling.  VCC rose just fine, but when they removed power for about a second, there were sometimes issues after reapplying power.  What was happening was that as VCC dropped, the Mclk vs VCC was violated while the chip was still running before the BOR reset the chip.  It took a while to figure out was going on, because I wasn't thinking about the falling side of the VCC.

    Thanks,

    JD     

         

  • JD,

    Thanks. And I agree with you.

    --OCY

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