MSP430FE427 - Timer A - Slowest count possible

Engrforever

Intellectual 480 points

Other Parts Discussed in Thread: MSP430FE427

Objective - I am trying to acquire the slowest timer count possible.
Environment
- Board: MSP430FE427
- IDE: IAR
Setup
- ACLK is 32Khz
- MCLK is 8 Mhz
Question
- I know I can use the ACLK as an input to the Timer_A input. Can I still divide the 32Khz ACLK to achieve a smaller timer clock?
- What would be the slowest count I can achieve?

over 15 years ago

0 Brandon08 over 15 years ago

TI__Mastermind 23415 points

Hi,

For this please refer to the block diagram at the beginning of the Timer_A chapter. Any of the clock inputs can be divided down, so you could have ACLK/8.

Now, if you are able to use external connections, you could output ACLK/8 using the FLL_DIVx bits (per section 5.2.9 of the Guide: http://focus.ti.com/lit/ug/slau056g/slau056g.pdf) on the ACLK pin, tie it to the TACLK input, and setup the timer using TACLK / 8, this way you make use of two sets of dividers (ACLK/8) /8

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MSP430FE427 - Timer A - Slowest count possible