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MSP430 and external ADS8327 via SPI, strange functionality

Genius 4170 points
Other Parts Discussed in Thread: MSP430F5437, ADS8327

Hello all,

first of all I opened another thread in the ADC forum here, but since there is almost no activity in comparison to this beautiful lively place I would like to ask for some help in here too.

The original post is placed here: http://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/233145/821740.aspx#821740

Now to explain the basic things:

I want to use an external ADC with 16 bit, since we got some troubles with the internal 12 bit ADC in the MSP430F5437, which I am using.

I am having a lot of issues not beeing able to correctly get data or recieve data from the ADS8327. Although some functions seem to work, so for example if i am sending 0xD000 to the ADC it will send back some data, which is also related to the voltage I connect at the IN+ pin of the ADS8327.

To make it more clear what is so strange:

My REF+ = 2,5 V

REF- = GND

So I would assume when I measure 0 V I get back 0000 0000 0000 0000, and when measuring 2,5 V or above I will get 1111 1111 1111 1111

What I do see is this:

0 ... 1,25 V -> 0x0000 ... 0xFFFF

1,251 V ... 2,5 V -> 0x0000 ... 0xFFFF

How ever in this world can this be? Am I having troubles with my external reference? I did measure it, although till now only with a handheld multimeter, but it didnt show anything else but 2,5 V so I assume its right, and anyway the behaviour is superstrange I think.

Next thing:

If I send the command for reading the config register 0xC0 I should get back something like 0xFFFD and I always get back 0xFFFE and this simply cannot be true in any world, since one of those bits is coupled to what hardware device it is and since I am using the ADS8327 there is always a 1 in one certain place... so I am really kind of confused.

So since I do not get any further with the trial and error I really would appreciate the help of someone already working with exactly this device and telling me if I am completly off the road, or if I am really close with what I am trying to do.

Thanks for reading and trying to understand my mind :)

Seb

  • It's possible that you have a wrong phase/polarity selected. As a result you miss the first bit and read the last one twice.

    The ADS seems to expect an idle-low clock (so default UCCKPL=0 is apparently correct) but I cannot tell about the phase. You should try again with UCCKPH set.

  • Thanks for the fast thoughts.

    Since my first SPI mode expirience with an Atmel Flash, I always simply start all 4 modes and look what is working for me. The datasheet states Mode 1 and Mode 2 should work which in my mind means. clock  = 1 phase = 0; or what also is possible is clock = 0and phase = 1.

    But again when I test all 4 modes and work with my saleae logic analyzer I get strange results, some modes seem to work more good than others and indeed something is always going wrong.

    So right now I try to read data into an array I do build so I really can see in the µC what data is being send from the ADS and if it is more right than my logic analyser, which I kind of distrust at the moment.

    So to conclude, since I am using all 4 SPI mode settings to send and receive data, it is definetly not them. I did test all 4 of them.

    No I am trying to work with the graph function of CCS 5.1 but since I never tried it it doesnt seem to work yet, or it is working but printing random numbers I guess :)

  • Well, if none of the 4 modes gives a reliable result, maybe it's time to put the logic analyzer away and use a scope to look at the real signal. maybe rise/fall times are so bad that MSP and logic analyzer have different ideas about what and when a signal is low or high.

  • I just did find some interesting statement in a MSP430 related blog:

    http://mspsci.blogspot.de/2012/09/tutorial-19b-usi-spi.html

    There the author states, in regard of the SPI-modes:

    There are four primary modes for SPI, depending on the signal's polarity (whether it idles high or low) and its phase (do we read when the clock is low and write when the clock is high, or vice-versa). Common notation for these two values are CPOL and CPHA, respectively. TI, however, uses the values CKPL and CKPH, with CKPH being inverted from the standard definitions for CPHA. (That is, if CPHA = 0, CKPH = 1 and if CPHA = 1, CKPH = 0.)

    So can anyone check if this is really true. As I have an Atmel Flash running with the same SPI bus I now wanna use for the external ADC, I did notice that TI and Atmel an probably some other chip vendors each have theit own definition of the SPI modes.

    But since this time I was using MSP430 from TI and the ADS8327 from TI I thought they might refer to the same SPI modes, but now I can read in the datasheet:

    CPOL and CPHA, which is confusing because the blog author says that CPHA is the inverted CPH which I have to set in my MSP430 registers.

    Now writing this I get even more confused :)

    Next step I will change my settings according to the blog, and I will look at the phase and clock manually ( still with the logic16 from saleae, because I am too lazy to bring the big haevy osciloscope to my desk :)

    Thanks for still following.

  • seb said:

    the clock is high, or vice-versa). Common notation for these two values are CPOL and CPHA, respectively. TI, however, uses the values CKPL and CKPH, with CKPH being inverted from the standard definitions for CPHA. (That is, if CPHA = 0, CKPH = 1 and if CPHA = 1, CKPH = 0.)

    Yes, that has been my observation -- to get CPHA=0 (according to the conventional terminology) you set UCCKPH=1. I once waded through the verbiage and confirmed that, but now I just do it out of habit. And TI also refers to SIMO/SOMI rather than MISO/MOSI (but you already knew that).

  • Bruce McKenney47378 said:
    to get CPHA=0 (according to the conventional terminology) you set UCCKPH=1.

    No, to get CPOL=0  you need UCCKPL=1. CPHA = 0 is UCCKPH=0.

    Teh TI naming makes some sense. It denotes the idle state of the clock. CKPL=0 means clock is idle low and active high. But I agree that for compatibility one could have chosen active state level instead.

  • Good morning.

    Jens could you please check that again, normally I trust your opinion, but this time I have to say I think you might be wrong.

    I give the SPI mode diagram from the Family User Guide:

    There you notice the CKPL indeed names the idle ( inactive ) condition of the clock signal ( this can also be really easy be seen on the logic analyser graphs, so I am pretty sure there is no confusion about those settings ).

    Now the "normal" CPOL I did only find some sources in english wikis, and elsewhere in the web, but there it is always the same as in the TI modes ( only speaking of the idle Clock signal ). If CPOL is 0 then the idle is low, when CPOL equals 1 it is idle high.

    Another thing that comes to my mind as I tested yesterday:

    I would say my Clock and enable and MOSI signals work pretty fine with my settings, what I always read wrong is the MISO line. I have the feeling I cannot be able to read it because its timing might be slightly off the clock, or perhaps exactly 1 half cycle. Could that be in for reasons perhaps the shift register is a little slower on the slaves side than on my MSP430 ( that would make sense in my mind at least).

    Because I assume the signals send back from the ADS are kind of euqal ( 1s and 0s at the same place, with a slightly phase shifted time component) but the logic analyser cannot read them properly because of that mentioned phase shift.

    MISO and MOSI seem to be shifted by half a clock cycle?!

    Next step is not reading with the logic analyser but with an array of somewhat 200 elements and then looking at the ADC counts coming from my  ADS and see if they make sense or not.

  • seb said:
    Jens could you please check that again, normally I trust your opinion, but this time I have to say I think you might be wrong.

    That's of course always a possibility.
    Actually, I don't care for 'mode' nubmers and check/compare the timing diagrams. As these are the things that count, no matter how they are named. So the info I posted was what I remember from older threads.

    I'm looking at a drawing in Wikipedia right now (which isn't error-proof either, but usually correct) and there indeed I see polarity the same as on TI and phase twisted. On CPHA=0, data is output before clock goes active. And on CKPH=1, it is clocked out when clock goes active. Which is opposite to the TI notation. However, when you switch polarity and phase, behaviour is the same except that the idle state changes: the first bit isn't output before the first clock edge and there is no final clock edge at which nothing happens. However, data output and data sampling appear in the correct order at the expected edges, if the clock line was fully initialized before the CS signal goes low. So mode 0 and 3 or 1 and 2 are usually exchangeable, even though some slaves may not like it.

    seb said:
    I would say my Clock and enable and MOSI signals work pretty fine with my settings,

    Well, MOSI and clock come form the same configuration and therefore shoudl alays fit :)
    It seems that your slave waits for the falling edge to output its data but doesn't output its data right when CS goe slow. The latter indicates that UCCKPH=0 is correct, but the first means that UCCKPL should be 1, so the first clock edge on which MISO and MOSI output the data is teh fallign edge from idle-high to active-low.

    However, if the firs tbit the slave outputs is a '1', then it is the opposite. The slave outputs the '1' when CS goes low, which indicates CKPH=1 and samples when clock is going active high. In this case Polarity is 0.

    Your analyzer output, however, shows that the USCI is running with CKPL=0 and CKPH=0.

    seb said:
    I have the feeling I cannot be able to read it because its timing might be slightly off the clock, or perhaps exactly 1 half cycle.

    If signals are output with too much delay form the clock edge or not held long enough after clock edge, then the swapping of polarity and phase won't work and only one mode will do. However, 1/2 clock cycle delay indicates a wrong phase  or right phase but wrong polarity.

    However, you wrote that none of the four modes gives a perfect result. So I'd say it's time to make a realtiem scope shot from the signal (triggered by the chip select) to see when exactly the edges happen.
    Also, MSP and logic analyter might have a different opinion about when a signal is low or high. Maybe you have a large line capacitance and lignals are rising/falling slowly.

    If you don't have a digital scope, using an ADC to sample the signal lines is a good substitute. However, 200 samples might still be a bit rough. (the analyzer already has 40 samples for the time enable=0) And of course you cannot use the ADS for this.

    I just took a look into the ADC datasheet and there it goes:

    "The internal data register content [...] is presented on the SDO output pin at the falling edge of FS/CS. This is the MSB. Output data are valid at the falling edge of SCLK with td(SCLKF–SDOVALID) delay so that the host processor can read it at the falling edge. Serial data input is also read with the falling edge of SCLK."

    So the required operating mode is CKPH=1 (data output when CS goes low without clock edge). However, the slave also seems to output on the falling edge, but with a small delay. While data is read at the falling edge.
    This is a rather strange setup, as the ADS seems to output its data and input it at the same clock edge, which rises serious timing problems if you have different line capacitances and the master samples at the clock edge instead of shortly after.
    After all, you have two clock edges (and a maximum clock speed) to ensure that when you output around one edge you have data stable aroudn the other.

    If you cannot minimize the delays on signal lines, I fear the only way for a reliable communication is to switch polarity between read and write (and hope that you never need to do both at the same time).

    It seems the ADS introduces a 'mode 4' operation here. :(

  • Thanks for that long interesting answer. I might test some others SPI mode settings again and write about it, but probably next year since I am off 2 weeks now :) hope that occurs to the rest of you as well.

    Yesterday, since I am distrusting my logicanalyser, but not my MSP430 with CCS debug mode, I did look at the incoming results in an array, like this ( not importnant only for interested:

        while (!(UCB1IFG & UCTXIFG));        //Sendepuffer bereit?
        UCB1TXBUF = 0xD0;                    // Read conversion result - 1101b
        while (!(UCB1IFG & UCRXIFG));        //Empfangspuffer bereit?
        Messergebnis = (unsigned int) (UCB1RXBUF<<8);
        while (!(UCB1IFG & UCTXIFG));        //Sendepuffer bereit?
        UCB1TXBUF = 0;                    // 8 Dont care bits übertragen
        while (!(UCB1IFG & UCRXIFG));        //Empfangspuffer bereit?
        Messergebnis |= UCB1RXBUF;
        while(UCB1STAT&UCBUSY);            // BUSY while TX or RX
        if (mess < 100 ){
            Messung[mess] = Messergebnis;
            mess++;
        }
        else{
            mess = 0;
        }

    Messung[mess] now has 100 values of 100 different measurments of hopefully the same constant voltage I apply via an external voltage source.

    And indeed these tests worked pretty fine, I did put on some voltages from 0...2 ,5 V and the ADS works really linear with only about under 1% of noise on the signal, which probably has some other reasons like my voltage reference my AVcc and Vcc ( with their ripples on) and so on.

    So I think I will only test clock and MOSI with the logic and simply do not look at the incoming signals any more.

    SPI reading without SPI sending at the same time unfortunatly is no option at all, since I do have to set commands and read along in the same time I fear.

    Next step will be to determine if the Config register read and write also applies, after that I will setup a routine for the ADS and try reading out my things in a certain time setting, and voila I will be finished forever :)

    Have a nice time everybody, till next year

  • seb said:
    since I am distrusting my logicanalyser, but not my MSP430 with CCS debug mode

    You shouild distrust both. But regarding different things :)

    Looking at your experient results, it seems that the logic analyzer is more strict regsarding the SPI timing and signal/clock correlation than the MSP. Lucky you that it works. However, it seems to be a bit shakey and I would check for thing slike line capacitance.

    Tonight, I suddenly had an idea: you might externally delay the SPI clock signal by adding capacitance or even an R/C compo. And change phase and/or polarity. This might shift the signal so that both, ADS and MSP, get the other ones data right.

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