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MSP430F167 as slave: will not ack own address

Other Parts Discussed in Thread: MSP430F167

Having trouble with  MSP430F167 as slave, because it will not recognize and ACK it's own address. I do get the start interrupt if enabled. But because of the errata I2C16 in http://www.ti.com/lit/er/slaz148a/slaz148a.pdf I have disabled start interrupt. My expectation, is that I would see the ack low on the 9th clock, and also get an OAIFG interrupt. Then the master would send or receive the next byte. I've tried several addresses and baud rates. without luck. I cannot see what is wrong. 

Can anyone see what I am missing, why is the I2C USART seeing Start condition, but not responding to a matching address? Thanks!

Init code:

void I2C_Port_EN(void) //***UART0 I2C Enable.***
{
P3SEL |= 0x0A; // Select I2C pins
U0CTL = I2C + SYNC + I2CEN; // II2 mode, slave
U0CTL &= ~I2CEN; // Must be disabled to set clock and address
I2CTCTL = I2CSSEL1; // SMCLK
I2COA = 0x007F; // Own Address , 7 bits right justified, high byte ignored.
I2CIE = TXRDYIE | RXRDYIE | OAIE | GCIE; // Enable TXRDYIFG interrupt
U0CTL |= I2CEN; // Enable I2C
}

 Here's the scope with SDA on top and SCL on bottom.

And the register states:

  • I don't have much experience with the USART I2C mode (I found it way too complex for my simple applicaiton, so I implemented a software I2C).

    But two things:

    0x7f isn't a valid slave address. 0000xxx and 1111xxx are reserved. But I doubt the I2C logic will care for this. However, 0000000 is the general call address and 11110xx is reserved for 10 bit addressing.

    The other thing is the shape of your waveforms. The slowly rising edge indicates that your pullups aren't strong enough. The maximum value depends on maximum bus capacitance. For a bus capacitance of 200pF, it should be <4k, for 400pF <2k. (with 1k being the minimum). This is for standard mode (100kHz max. clock). For high-speed, maximum pullup resistance is even lower.
    Maybe these 'sharkfin' signal edges are the reason for your problems.

  • SOLVED.

    Thanks for the ideas. They led me in the right direction, but for the record, the issues was the time between Start and SCLK7 was too short. 

    15.2.6
    Note: I2CCLK Maximum Frequency
    I2CIN must be at least 10x the SCL frequency x the I2CPSC divider rate in
    both master and slave modes. For example, with an I2CPSC value of 02h,
    I2CIN must be > 3 kHz x 3 x 10, or > 90 Khz for a 3-kHz SCL
    And Figure 15-12  STTIFG is set, then 4x I2CPSC cycles elapse, then I2CBB is set and address receiver is armed. 

    So even though this is a sync USART, the internal clockrate still matters for the slave since the state machine does not wake up the receiver after the start condition until 4 clocks have passed. 

    I was running on the slowest DCO frequency, which caused the problem. At the fastest DCO rate I can run at 97K baud. 

    The rising edge lag is just a result of my cheap probe cables, and the 7F address also works even though it may be reserved,  but neither were a problem.

  • Mike Mitchell1 said:
    The rising edge lag is just a result of my cheap probe cables

    I wonder why the falling edge is so steep then. Except if your cables have a high serial resistance and the scope has a low input impedance :)

    Mike Mitchell1 said:
    So even though this is a sync USART, the internal clockrate still matters for the slave

    Apparently. On the USART, this isn't the case, you don't need an internal clock for slave operation. And the USI, which isn't much more than a shift register, this doesn't seem to be a problem too.

    So I was even more lucky to not use the USART I2C mode ever (even though my devices all run on 4 or 8 MHz).

    Mike Mitchell1 said:
    until 4 clocks have passed. 

    hmmm, if I2CPSC is 0, this means a clock divider of 1, but isn't "4*I2CPSC" == 0 then? Or should 15-12 rather read  " 4* (I2CPSC+1) "?

    Mike Mitchell1 said:
    At the fastest DCO rate I can run at 97K baud. 

    Isn't the fastest DCO rate 5-6MHz? You should be able to run 400kbps easily (after all, teh users guide specifies compliance with 400kpbs fast mode and doesn't restrict it to master operation)

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