ESD/EMI protection for MSP430 JTAG pins

Why do you need to add ESD/EMI protection to debug connector? It supposedly is not accessible to user while device in use.

Jens-Michael Gross said:

Is it ok to add buffers to the JTAG pins?

It is not a good idea to add a buffer[/quote]

Exactly. Primary function of buffer is buffering, not ESD protection. This kind of devices shall be used instead:

http://www.semtech.com/circuit-protection/low-voltage-esd-protection/

If you are actually worried about noise on the TEST pin (not really ESD) potentially causing the part to enter JTAG/BSL/SBW mode by accident, you can put a pull-down resistor on TEST. See this thread: http://e2e.ti.com/support/microcontrollers/msp430/f/166/t/286094.aspx 

Regards,

Katie

Thank you so much for the suggestions.

Actually our customer's debug environment seems to be susceptible to
noise and static electricity which has destroyed few devices.
So as per your suggestions, we shall try to use ESD/EMI protection diodes instead of buffer.

Katie Enderle Pier said:

If you are actually worried about noise on the TEST pin (not really ESD) potentially causing the part to enter JTAG/BSL/SBW mode by accident, you can put a pull-down resistor on TEST

The TEST pin has internal ~50k pulldown, which should be sufficient for most cases. In extremely noisy environment, an additional pulldown of 4,7k might be required. However, this won't protect against ESD events, where a high voltage peak will likely extend beyond teh input threshold (and sinked to GND by the clamp diodes when exceeding VCC).

Ilmars said:

Primary function of buffer is buffering, not ESD protection.

Indeed. But many buffers have integrated ESD protection, and also may srve as noice cancellation device (e.g. schmidt-trigger input). So one could be tempted. But then, things like propagation delays and signal direction must of course be considered.
For the JTAG pins, a buffer is not suitable for more than one reason.

Jens-Michael Gross said:

In extremely noisy environment, an additional pulldown of 4,7k might be required.

True - that is definitely the only cases I've seen this needed for - one I can think of had a relay that produced a lot of noise in addition to a really long trace on the TEST pin that would pick up noise.

As a follow up to this thread, can I just ask what to do when we have seen a lot of these problems in already shipped devices.

The problem is that we have seen a lot of RMA'ed devices where we suspect problems with accidental entering program/test mode. Now since we cannot exchange the HW, simply because of the scale, I would like to ask whether it would help us to blow the fuse.

We can all agree that the design needs fixing, adding pulldown and reducing TEST/RST pin traces, but would blowing the fuse guarantee that the MCU would never enter SBW/JTAG mode accidentally?

Thanks in advance

Thomas Bowley

Thomas Bowley said:

would blowing the fuse guarantee that the MCU would never enter SBW/JTAG mode accidentally?

On devices with an electrical JTAG fuse (1x,2x, 4x family) it should. The JTAG circuit  will not accept any more command than JTAG_BYPASS. However, JTAG will still be active. The TEST pin, tied high, will still switch the PORTJ pins to JTAG mode. and erratic signals on SBWTCK/SBWTDIO will will turn the RST pin into SBW pin mode (preventing a hardware reset) But there shouldn't be any influence on the CPU core anymore.

On 5x family, the 'fuse' is a software fuse that is checked during boot code execution. Here, IIRC JTAG is inactive by default and only activated by the boot code if the JTAG fuse is 'intact'. Again, I don't think it will influence the electrical effects of entering JTAG mode. I twill only prevent JTAG from issuing any commands to the CPU/memory/EEM

But don't take this as an authoritative answer.

Hi Thomas,

I will check with our tools experts about your suggested workaround for a case where hardware can't be changed, to see if they think it would work. Which MSP430 device do you use (I'm not sure if it will matter but it might because of different fuse implementation as Jens-Michael mentioned).

At the least, if you use MUX'd JTAG pins for other functions, TEST is going to affect those pins' configuration no matter what (see the GPIO diagrams for these in the datasheet), so if you are using those you are likely to have issues as Jens-Michael pointed out. I'll see about what happens if you don't use those and are just wondering about entering JTAG mode by accident. I'm still doubtful though because pulses on TEST/RST could also make you enter BSL mode, not just JTAG/SBW.

Regards,

Katie

Hi Katie

We use the F2001 but are looking at transcending to the G-series, so if anything is different in the matter of TEST/RST and accidental JTAG/SBW/BSL mode.

Since it is a very low pin count (14) chip we use, yes the JTAG port pins are also used for GPIO's during normal application run.

I just didn't know where to look for tha GPIO diagrams that you mention, that also includes the JTAG circuitry.
Also, it seems I have forgotten to think about the BSL mode.

Seems like there is no way around a new hardware spin and then handling the RMA's on the old HW.

Looking forward to the answer from the tools expert.

regards

Thomas

Hi Katie

Thank you so much for your help, although it was bad news to us.

We've certainly learned a hard lesson in HW design regarding the RST/TEST pins on the MSP430.

Best regards

Thomas

PS:
It seems like I cannot verify your answer since the post has already been verified, is that correct? 

Thomas Bowley said:

PS:
It seems like I cannot verify your answer since the post has already been verified, is that correct? 

It's because only the original poster and moderators can verify answers and this was a continuation of a previous thread. But since you said that it answers your question I will mark it myself.

Thomas Bowley said:

We've certainly learned a hard lesson in HW design regarding the RST/TEST pins on the MSP430.

Now you know why many PCBs have so many unpopulated pads for resistors and capacitors. Placed there, just to be sure, and left away when it was clear that they aren't needed. You can always chose to not populate parts that are planned. It is way more difficult to add parts that have not been planned.
In my designs, I even reserve some space for series resistors (populated with 0Ohms resistors or a drop of lead) when there is the faintest chance I'll need it.

Thomas Bowley said:

It seems like I cannot verify your answer since the post has already been verified, is that correct? 

No, you can verify (and un-verify) and number of posts. But this is restricted to the thread starter.
One more reason to start a new thread for a new question (preferrably with a reference to the old thread) :)