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evaluation board for MSP430F5232

Jason Kang
Intellectual 470 points
Other Parts Discussed in Thread: MSP430F5232, MSP430WARE

Hi, 

I am going to use MSP430F5232 for my design, and I need to purchase its evaluation board.

What I could find is MSP-FET430U64C. It seems to be a good candidate, but it is for 64-pin package.

I have two questions.   

1. Do you have an evaluation board only for MSP430F5232 (48-pin package)?

2. If not, what evaluation board do you recommend?

Thank you. 

  • 0
    TI__Mastermind 21285 points

    Hello Ji-Won,

    Section 1.12 of SLAU278 includes a large table that breaks down the supported devices for each MSP430 target board.  Searching for the F523x shows that only the 64-pin RGC packaged device has an associated target board.  So to answer your questions;

    1) unfortunately, no.

    2)  The kit you have found is the recommended one.

  • 0 in reply to Michael S
    Intellectual 470 points

    Thank you for your quick feedback.

    Have a nice day. 

  • 0 in reply to Michael S
    Intellectual 470 points

    I have another question.

    From MSP430F5232, I want to use one SPI & two I2C as shown below.

    • PA: P1.x 1x8 I/O: p1.0(MC_SCLK), p1.1(MC_MOSI), p1.2(MC_MISO), p1.3(MC_NCS).
    • PA: P2.x 1x1 I/O
    • PB: P3.x 1x5 I/O: P3.0(MC_SDA_1), p3.1(MC_SCL_1)
    • PB: P4.x 1x7 I/O: P4.1(MC_SDA_2), P4.2(MC_SCL_2)
    • PC: P5.x 1x6 I/O
    • PC: P6.x 1x6 I/O
    • PJ: PJ.x 1x4 I/O

    In the above plan, please note that P3 will be used as a master while P4 is a slave.  

    Can the P3 and P4 share the same I2C channel?

    In other words, can MC_SDA_1 and MC_SDA_2 share the same line while MC_SSL_1 and MC_SCL_2 are tied together?

    Of course, only one I2C will be active at a certain time.

    Thank you.  

  • 0 in reply to Jason Kang
    TI__Mastermind 21285 points

    I cannot think of a reason why you would not be able to have the MSP430 with a master and slave channel on the same bus.  I presume that the MSP430 would be configured into a multi-master mode of operation?

  • 0 in reply to Michael S
    Intellectual 470 points

    Yes, you are correct. 

    Either MSP430F5 or an FPGA will be the master. 

    When the FPGA is a master, MSP430F5 will be one of the slaves. 

  • 0 in reply to Michael S
    Intellectual 470 points

    Yes, you are correct. 

    Either MSP430F5 or an FPGA will be the master. 

    When the FPGA is a master, MSP430F5 will be one of the slaves. 

  • 0 in reply to Jason Kang
    TI__Mastermind 21285 points

    Hi Jason,

    If memory serves, multi-master not only covers the bus arbitration but also the capability of a device operating in multi-master mode to be addressed directly by another multi-master capable device.  With that being said, you should not need to use 2 separate I2C channels.  The documentation discusses the requirement for a device operating in multi-master mode is required to be given an address of it's own which is to be programmed into the UCBxI2COA register. 

    Multi-master is, relatively speaking, an uncommon implementation and I've not seen demo code within MSP430Ware illustrating multi-master functionality.

  • 0 in reply to Michael S
    Intellectual 470 points

    Hi, Michael.

    In short, are you saying that one I2C channel can be configured as either master or slave & it can be changed to the other while the chip is in operation?

    In that case, are you also suggesting that only one I2C channel is to be used instead of two I2C channels?

    By the way, I want to clarify something. 

    Please note that there will be only one master at a time in my system.

    In other words, either MSP430F5 or an FPGA will be a master. 

    In that case, can it be still considered as a multi-master?

    Thank you. 

  • 0 in reply to Jason Kang
    TI__Mastermind 21285 points

    In short, are you saying that one I2C channel can be configured as either master or slave & it can be changed to the other while the chip is in operation?

    That is one option.  The other option is to configure the MSP430 for multi-master mode of operation.  The FPGA also needs to support multi-master mode as well for this to work.

    In that case, are you also suggesting that only one I2C channel is to be used instead of two I2C channels?

    In both cases, yes.  Granted, the only thing that you save, is a small amount of copper trace but there is a degree of complexity added since, as I mentioned previously, I've not seen any multi-master demo code for our MSP430 devices.

    By the way, I want to clarify something. Please note that there will be only one master at a time in my system.  In other words, either MSP430F5 or an FPGA will be a master.  In that case, can it be still considered as a multi-master?

    If you configure both devices as masters that support multi-master operation, then it is considered a multi-master use case.  If you configure one as master, the other as a slave and exchange the roles of each device via firmware configuration, then it is not considered multi-master as there is only one master at any given time.

  • 0 in reply to Michael S
    Guru 227245 points

    Michael S said:
    The FPGA also needs to support multi-master mode as well for this to work.

    At least it has to be multi-master aware, which measn that it doe snot assume it can simply use the bus as nobody else will ever start a transfer there. it does not have to support being a slave (if not required by application).

    The users guide coves the process of bus arbitration that must be supported by any master device on the same bus if there are ever more than one master.

    Michael S said:
    , the only thing that you save, is a small amount of copper trace

    And two pull-up resistors :)

    Michael S said:
    By the way, I want to clarify something. Please note that there will be only one master at a time in my system.  In other words, either MSP430F5 or an FPGA will be a master.  In that case, can it be still considered as a multi-master?

    [/quote]Depends. If the two have other means to notify each other of which one is the master now, then it is not necessary. They have to (externally, not by I2C) agree which one is the master now and which one must not access the bus (as master).

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