USART in SPI mode send MOSI as UART

Artem Kashkanov

Other Parts Discussed in Thread: MSP430FE4252

Hi!

I'm using MSP430FE4252 in my project. And I need to connect it to the display via SPI.

At first I configure USART module:

//setup USART0 in SPI mode
    LCD_MOSI_SEL |= LCD_MOSI_PIN;
    LCD_CLK_SEL |= LCD_CLK_PIN;


    UBR00 = 0x02;// set baud divide by two
    UBR10 = 0x00;

    U0CTL |= SWRST;//Reset
    U0ME |= USPIE0;//switch On SPI module
    U0CTL |= SYNC + CHAR + MM;//SPI 8 bit Master Mode
    U0TCTL |= STC;//3-pin SPI mode
    U0TCTL |= SSEL1;//use MCLK
    U0CTL &= ~(SWRST);//Rest Done

And send to display comand and data without interrupts:

void WriteCommand(uint8_t ucData)
{
    // Store current GIE state
   uint16_t gie = __get_SR_register() & GIE;
    // Make this operation atomic
   __disable_interrupt();
     ClearCS();
    LCD_CD_PORT &= ~LCD_CD_PIN;
      while(! (U0TCTL & TXEPT));
       U0TXBUF = ucData;
          while(! (U0TCTL & TXEPT) );
   // CS High
    SetCS();
    // Restore original GIE state
   __bis_SR_register(gie);
   __enable_interrupt();
}

Start Debug (CCS V5.5) via MSP30FET and via Logic Analyzer watch next picture

WAT? Inverse Logic in MOSI signal and additional bits in It (there are 12 bits in CLK signal)..

Pause Debug and looking through registers:

All is good (as I think). SPI mode, in U0TCTL CKPH and CKPL are equals zero..

On some other MCU-s USCI module with ~same config works well..

What I need to do to have normal MOSI signal?

PS: I tried to reset U0MCTL with the same result

over 12 years ago

0 Jens-Michael Gross over 12 years ago

Guru 227245 points

I don’t see 12 clock pulses per byte. The blocks are only 8 clock pulses long (apparently, the SPI clock speed is in the range of your analyzer’s sampling rate, resulting in some clock pulses shown with double width).

I can’t confirm any inverse logic, as the code you posted just sends ‘ucData’ from an unknown source and with unknown value. MOSI could output anything.

CKPL=0 means the clock is active-high and idle-low. This is opposite to the Motorola notation where polarity=0 means idle-high and active-low (the more usual version, as in the old TTL world, inputs were high by internal pull-ups, unless actively pulled low).

I wonder why MOSI changes state after some time (without any clock). But then again, since the surrounding code is unknown, I cannot say whether this is an anomaly or caused by the code.

0 Artem Kashkanov over 12 years ago in reply to Jens-Michael Gross

Prodigy 30 points

I clear all questions and now display works.

1. 12 pulses per byte was not NULL modulate register - U0MCTL It only recommended to clear in SPI mode, but I set it to zero, and now clock is good.

2. There is no inverse logic, but MOSI in idle state is realy set HIGH, and some time after last bit it setet to HIGH. I tried to rule by registers, but had no effect.

3. On my display - WX12864U1 - inputs data with rising clock and U0TCTL |= CKPH helps.

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USART in SPI mode send MOSI as UART