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query about usaing timer as counter

Other Parts Discussed in Thread: MSP430FR5729

i have controller msp430fr5729. i use timer A0 as counter to count external pulse.

my question is that suppose my counter overflow. i am in isr routine of A0 and that time external pulse come. so this pulse is noticed by counter or not?

  • The timer module is a peripheral attached to the CPU core, so it continues to operate regardless of the fact that the CPU is executing code in the ISR. (The timer doesn't know what the CPU is executing).

    The timer will capture the event. However, you won't get an interrupt for it until after the CPU exits the currently executing ISR. You will still get the interrupt though (assuming everything is configured correctly).

  • thats a interesting question, I am looking for the answer too. 
    my speculation would be like, 
    1. you are detecting pulses from port interrupts (I hope) and then count them by counter.
    2. Id say you will get that pulse by port and might miss counting that pulse.( unless you clear TAIFG of timer A0)

  • There are many different ways to “count an external pulse”.

    The original post seems to indicate that one of the 5 hardware Timers is used to count the external pulse. In that case, Brian already answered the question,

    You seem to assume that the external pulse is used to generate a Port Pin interrupt, and the ISR is used to count in software.  In that case, you are right too.

  • i am implementing flow meter. i have two external pulse input and i give both to 2 different timer clock and take interrupt at overflow. when counter overflow i add pulse in total value. so i think problem occur when i serving one counter overflow interrupt and that time second counter overflow... so can i enable interrupt while i am in isr of one counter i mean nesting of interrupt???

    and one another thing i want to know is that, what actually happen when i read counter resister?

    because in some micro controller when we read counter resister what happen is that

    1- timer/counter stop

    2- link current value

    3-timer/counter start again

    so what in our case?????? 

  • The timer doesn’t stop counting pulses on an overflow. It just sets the overflow interrupt bit and continues. Pulses are counted in hardware and this operation is independent of the current code execution.

    However, if you are using the CCR capture interrupts to detect a pulse, you may miss the second pulse interrupt (for the same counter) if you haven’t already handled the first one (or at least cleared the IFG bit before the second pulse).
    If you are serving the overflow of one timer while another tiemr overflows, theis second interrupt is buffered and handled as soon as you leave the ISR of the first.
    You have a complete timer cycle to handle the overflow interrupt befiore you get another one on the same timer. Which is normally plenty of time.

  • You would not lose count when you handle counter overflow interrupt. You would not lose count when the CPU is handling other interrupt (or even during CPUOFF). The counter keeps counting unless you change the Timer control register or its input.

    Reading the counter would not change its counting activity either. However, since your CPU is asynchronous with the external pulse, theoretically there is a very small chance that the reading could be wrong. But the counter itself stays correct.

  • thank you all for answers..

  • Thank you JMG and OCY

  • >one counter overflow interrupt and that time second counter overflow...

    Why would you miss it? they are on separate TAxIV registers.
    If for example it takes 1second on average for a counter to overflow, you have one second to service that routine.
    If the second counter overflows while you service ISR1 (and as a service routines should be less than 10uS)
    the Flag will be there when you exit and the ISR2 will be invoked right away.

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