I can not seem to have the SCLK signal held low when operating in the slave I2C mode. The I2C communications run fine, but I need to introduce a SCLK clock stretch when 'reading/writing' data. After detecting the read operation, where I set an external 'process state' to handle the reading of the appropriate data, the SCLK is held low until I execute the 'USICTL1 &= ~USIIFG' line the clock line is released (returned high). How do I keep the clock low until I reload the USICNT register?
case XMIT_DATA: // Check ACK and send next byte
if (USISRL & 1) { // Check if NACK
u8_USI_InterruptState = WAIT_START;
}
else {
u8_USI_ProcessState = READDATA; // a read request, do not load USICNT
}
break;
case XMIT_DATA_ACK: // Setup to Receive ACK
USICTL0 &= ~USIOE; // SDA = input
u8_USI_InterruptState = XMIT_DATA; // On next CLK\ check ACK & setup for reading next byte
USICNT |= 0x01; // Bit counter = 1, receive Ack
break;
}
USICTL1 &= ~USIIFG; // Clear pending flags
}
