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MSP430F5436 RTC Timing Issue

Hi,

We observe that the timing of units are drifting more than normal. Some of the units are slower while other units run faster than the correct time. The sample size is 5 units. 

We make use of the MSP430's RTC_A module for time keeping. Also we have an external 32.768 KHz Crystal connected to XIN/XOUT (Pin 13 & 14) and use it as source for XT1 in LF mode. 

The crystal spec is below.

Can you let us know what could be contributing to this timing drift? Any pointers on what is to be taken care of from software/registers point of view  Do let us know if you need any other information.

  • The 5436 uses ACLK (or SMCLK, of you want) as clock source.
    So it is important that you configure ACLK correctly.
    Maybe you do not properly fire-up the crystal. If you get an oscillator fault (or fail to properly handle the initial fault at power-up), then ALCK runs from the internal REFO, which has a rather large variation across different devices.
    You should post your clock system setup code.

  • Hi Jens,

     

    Thanks for your kind reply, pls see below code and help advise anything is not done correctly?

     

    bool ClockDriver::InitBootClocks()

    {

        EnableXT1ClockPins();

     

        // XT2DRIVE = level unchanged, XT2 = unchanged, XT1DRIVE = highest, XTS = LF, XT1 = internal source, SMCLK = off, XT1 = on

        //UCSCTL6 = (UCSCTL6 & (XT2DRIVE_3 | XT2OFF)) | XT2DRIVE_1 | XT1DRIVE_3 | XCAP_0 | SMCLKOFF;

        UCSCTL6 = (UCSCTL6 & (XT2DRIVE_3 | XT2OFF)) | XT2DRIVE_1 | XT1DRIVE_3 | XCAP_1 | SMCLKOFF;

     

        // Wait for XT1 in LF mode to settle

        bool success = ClockSettleWait(XT1LFOFFG);

     

        // Will be automatically configured by FLL

        UCSCTL0 = 0x0000;

     

     

        // FLL core frequency configured to support 8 MHz. DCO modulation disabled.

        UCSCTL1 = DCORSEL2 | DCORSEL1 | DISMOD;

     

        // Set FLL divider and multiplier

        UCSCTL2 = ((static_log<BOOT_FLLD,2>::result) << 12) | (BOOT_FLLN);

     

        // Use XT1 as the DCO reference clock

        UCSCTL3 = SELREF__XT1CLK | (static_log<FLLREFDIV,2>::result);

     

        // ACLK source = XT1CLK, SMCLK source = DCODIV, MCLK source = DCODIV

        UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV;

     

        // Disable XT2

        //UCSCTL6 = XT2DRIVE_0 | XT2OFF | XT1DRIVE_3 | XCAP_0;

        UCSCTL6 = XT2DRIVE_0 | XT2OFF | XT1DRIVE_3 | XCAP_1;

     

        // Configure ACLK, SMCLK, and MCLK source divider

        UCSCTL5 = DIVPA__1 | DIVA__1 | ((static_log<BOOT_SMCLK_DIVIDER,2>::result) << 4) | (static_log<BOOT_MCLK_DIVIDER,2>::result);

     

        // Clear oscillator fault flags

        UCSCTL7 = 0x0F00;

     

        // MODOSC Request Disabled, SMCLK Request Enabled, MCLK Request Enabled, ACLK Request Enabled

        UCSCTL8 = 0x0700 | SMCLKREQEN | MCLKREQEN | ACLKREQEN;

     

        // Wait for oscillator fault conditions to clear

        success = success && FaultClearWait();

     

        // Decrease XT1 drive strength after clocks settle. Disable XT2. Disable SMCLK.

        //UCSCTL6 = XT2DRIVE_0 | XT2OFF | XT1DRIVE_1 | XCAP_0 | SMCLKOFF;

        UCSCTL6 = XT2DRIVE_0 | XT2OFF | XT1DRIVE_1 | XCAP_1 | SMCLKOFF;

        DisableXT2ClockPins();

     

        // Decrease core voltage when running on low power clock

        PMM_DisableLowPowerPOR();

        success = (SetVCore(0) == PMM_STATUS_OK) && success;

        PMM_EnableAutoLowPowerMode();

     

        if (success)

        {

            m_state = StateBoot;

        }

        else

        {

            m_state = StateNotInitialized;

        }

     

        return success;

    }  

     

  • Take a look at the RTC example - msp430f66xx_rtc_01.c - I would also add the RTCCLK (P5.7) output to see what your RTCCLK looks like, and you can then add any optional calibration to get your clock running "like a clock..."

    One of the things that I have found is once in awhile I get an XT1 oscillator fault. When that happens, the ACLK reverts to REFO, which is not nearly 32768 Hz....

    Hopefully, that helps.

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