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Few questions about design user application board based on msp430f5256

Denis Shashunkin
Prodigy 100 points
Other Parts Discussed in Thread: MSP430F5256

Hi all!

I`m designing board based on msp430f5256.

And I have some question about schematics.

 

1. about split-supply I/O

If I don`t using mcu i/o port supply from DVIO domain.

Can I don`t connect DVIO pin to 1,8 V power supply? or DVIO need 1,8 V power supply always?

2. about VeREF

If I don`t using ADC. How correct connect VeREF+ and VeREF- pins. Or it does not have anywhere to connect?

3. about RESET

If I don`t usind BSL and RST/NMI pin that pool-down by default.

Can I don`t connect RST/NMI and reseting MCU by RSTDVCC?

4. about external XT2

If I use external XT2, how connect XTIN and XTOUT pins? Or XTIN and XTOUT pins does not have anywhere to connect?

5. about consume of MCU

How much msp430f5256 consume if it using the following:

- it work in active mode

- external quartz 20MHz

- four USCI on UART mode

- using 3-4 pio

- using DMA

 

Thanks!

  • 0
    Guru 227245 points

    1. From Datasheet: Voltage applied to Vio: -0.3V to 2.2V. So connecting Vio to Vss is in the allowed range. Note that allowed input voltage to any I/O pin of Vio domain is then +-0.3V (so connect them to Vss too.

    2. Veref is connected to the ADC through an analog switch. If not used, (switch open), the pins are like any other I/O pin (P5.0/P5.1) and should be set to low output (or tied to Vss) if not used, to reduce power consumption.

    3. RST has an internal pull-up that is active by default. However, it is recommended to add a small capacitor to Vss, to make up for a slowly rising (non-ideal) supply. When using SBW protocol, the maximum capacitance is limited to 2.2nF, if not, 100nF are a common choice.

    4. XIN/XOUT can be switched to GPIO mode (P5.4/P5.5; IIRC, this is the default anyway) and should be handled like any other I/O pin if not used. P5.2/P5.3 need to be switched to module, and besides the crystal, the required load capacitors need to be applied.

    5. See details in the datasheet. I don’t have any more information that what is stated there. DMA is like the CPU executing a MOV command in active mode. Just without reading the instruction and the source/destination address from flash. Power consumed for PIO mode depends on the load on the I/O pins. Same for USCI (usually, the output current is higher than the internal currents) Basically, all internal current depends on the number of state changes per second, since on CMOS technology, no constant current is drawn, but a certain charge is required to change a gate state. No state change, no current.

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